Symbol: psr
sys/arch/arm/include/armreg.h
131
#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
sys/arch/arm64/dev/rtkit.c
332
uint64_t psr;
sys/arch/arm64/dev/rtkit.c
413
printf("RTKit Crg8: psr %016llx\n", rg8.psr);
sys/arch/luna88k/include/cpu.h
22
u_long psr;
sys/arch/luna88k/include/cpu.h
24
psr = get_psr();
sys/arch/luna88k/include/cpu.h
25
set_psr(psr | PSR_IND);
sys/arch/luna88k/include/cpu.h
26
return psr;
sys/arch/luna88k/include/cpu.h
30
intr_restore(u_long psr)
sys/arch/luna88k/include/cpu.h
32
set_psr(psr);
sys/arch/luna88k/luna88k/machdep.c
1196
uint32_t psr;
sys/arch/luna88k/luna88k/machdep.c
1199
psr = get_psr();
sys/arch/luna88k/luna88k/machdep.c
1200
set_psr(psr | PSR_IND);
sys/arch/luna88k/luna88k/machdep.c
1205
set_psr(psr);
sys/arch/luna88k/luna88k/machdep.c
1213
uint32_t psr;
sys/arch/luna88k/luna88k/machdep.c
1216
psr = get_psr();
sys/arch/luna88k/luna88k/machdep.c
1217
set_psr(psr | PSR_IND);
sys/arch/luna88k/luna88k/machdep.c
1223
set_psr(psr);
sys/arch/m88k/include/asm_macro.h
47
set_psr(u_int psr)
sys/arch/m88k/include/asm_macro.h
49
__asm__ volatile ("stcr %0, %%cr1" :: "r" (psr));
sys/arch/m88k/include/asm_macro.h
59
u_int psr;
sys/arch/m88k/include/asm_macro.h
60
__asm__ volatile ("ldcr %0, %%cr1" : "=r" (psr));
sys/arch/m88k/include/asm_macro.h
61
return (psr);
sys/arch/m88k/include/atomic.h
102
u_int psr;
sys/arch/m88k/include/atomic.h
105
psr = get_psr();
sys/arch/m88k/include/atomic.h
106
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
109
set_psr(psr);
sys/arch/m88k/include/atomic.h
34
u_int psr;
sys/arch/m88k/include/atomic.h
36
psr = get_psr();
sys/arch/m88k/include/atomic.h
37
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
39
set_psr(psr);
sys/arch/m88k/include/atomic.h
45
u_int psr;
sys/arch/m88k/include/atomic.h
47
psr = get_psr();
sys/arch/m88k/include/atomic.h
48
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
50
set_psr(psr);
sys/arch/m88k/include/atomic.h
56
u_int psr;
sys/arch/m88k/include/atomic.h
59
psr = get_psr();
sys/arch/m88k/include/atomic.h
60
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
63
set_psr(psr);
sys/arch/m88k/include/atomic.h
71
u_int psr;
sys/arch/m88k/include/atomic.h
74
psr = get_psr();
sys/arch/m88k/include/atomic.h
75
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
78
set_psr(psr);
sys/arch/m88k/include/atomic.h
86
u_int psr;
sys/arch/m88k/include/atomic.h
89
psr = get_psr();
sys/arch/m88k/include/atomic.h
90
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
94
set_psr(psr);
sys/arch/m88k/include/cpu.h
109
(uint32_t psr, __cpu_simple_lock_t *lock, uint csr);
sys/arch/m88k/m88k/m88100_machdep.c
351
uint32_t psr;
sys/arch/m88k/m88k/m88100_machdep.c
353
psr = get_psr();
sys/arch/m88k/m88k/m88100_machdep.c
354
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m88100_machdep.c
357
return psr;
sys/arch/m88k/m88k/m88100_machdep.c
361
m88100_mp_atomic_end(uint32_t psr, __cpu_simple_lock_t *lock, uint csr)
sys/arch/m88k/m88k/m88100_machdep.c
364
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
1047
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
1093
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
1094
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
1178
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
786
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
794
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
795
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
799
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
809
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
816
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
817
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
821
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
827
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
834
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
835
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
839
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
845
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
852
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
853
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
857
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
882
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
893
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
894
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
913
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
922
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
933
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
934
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
953
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
962
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
973
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
974
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
993
set_psr(psr);
sys/arch/m88k/m88k/process_machdep.c
85
unsigned int psr = procregs->epsr;
sys/arch/m88k/m88k/process_machdep.c
89
(psr & PSR_USERSTATIC) | (regs->epsr & ~PSR_USERSTATIC);
sys/arch/m88k/m88k/trap.c
230
u_int psr;
sys/arch/m88k/m88k/trap.c
258
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
260
set_psr(psr);
sys/arch/m88k/m88k/trap.c
265
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
267
set_psr(psr);
sys/arch/m88k/m88k/trap.c
630
u_int psr;
sys/arch/m88k/m88k/trap.c
724
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
726
set_psr(psr);
sys/arch/m88k/m88k/trap.c
731
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
733
set_psr(psr);
sys/arch/m88k/m88k/trap.c
738
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
740
set_psr(psr);
sys/arch/macppc/macppc/cpu.c
124
u_int64_t psr;
sys/arch/macppc/macppc/cpu.c
142
psr = ppc64_mfscomd();
sys/arch/macppc/macppc/cpu.c
144
if (psr & PSR_CMD_COMPLETED)
sys/arch/macppc/macppc/cpu.c
147
} while (psr & PSR_CMD_RECEIVED);
sys/arch/macppc/macppc/cpu.c
149
if ((psr & PSR_FREQ_MASK) == PSR_FREQ_HALF)
sys/arch/macppc/macppc/cpu.c
324
u_int64_t psr;
sys/arch/macppc/macppc/cpu.c
329
psr = ppc64_mfscomd();
sys/arch/macppc/macppc/cpu.c
333
if ((psr & PSR_FREQ_MASK) == PSR_FREQ_HALF) {
sys/dev/acpi/acpiac.c
131
int64_t psr;
sys/dev/acpi/acpiac.c
133
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "_PSR", 0, NULL, &psr)) {
sys/dev/acpi/acpiac.c
138
sc->sc_ac_stat = psr;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9647
struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9656
else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9657
!psr->psr_feature_enabled)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9664
(psr->psr_feature_enabled || pr->config.replay_supported)) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9683
(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9686
if (psr->psr_version == DC_PSR_VERSION_SU_1 &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9687
!psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
312
struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
314
bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
92
if (link->panel_config.psr.disallow_replay)
sys/dev/pci/drm/amd/display/dc/dc.h
269
bool psr;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1222
} psr;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
480
static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
482
psr->ctx = ctx;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
483
psr->funcs = &psr_funcs;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
491
struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
493
if (psr == NULL) {
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
498
dmub_psr_construct(psr, ctx);
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
500
return psr;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1088
link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
597
link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
628
link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
826
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
277
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
988
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
315
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
575
bool is_psr = link && !link->panel_config.psr.disable_psr &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
358
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
320
struct dmub_psr *psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
589
struct dmub_psr *psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
592
if (psr == NULL && force_static)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
607
if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
608
psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
611
if (psr != NULL && link->psr_settings.psr_feature_enabled &&
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
612
force_static && psr->funcs->psr_force_static)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
613
psr->funcs->psr_force_static(psr, panel_inst);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
622
if (psr != NULL && link->psr_settings.psr_feature_enabled) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
623
psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
637
struct dmub_psr *psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
643
if (psr != NULL && link->psr_settings.psr_feature_enabled)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
644
psr->funcs->psr_get_state(psr, state, panel_inst);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
694
struct dmub_psr *psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
711
if (link->panel_config.psr.read_psrcap_again) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
734
psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
736
if (!dmcu && !psr)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
889
if (psr) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
890
link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
911
struct dmub_psr *psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
918
if (psr != NULL && link->psr_settings.psr_feature_enabled)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
919
psr->funcs->psr_get_residency(psr, residency, panel_inst, mode);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
926
struct dmub_psr *psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
928
if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
931
psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1532
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1534
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
634
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
756
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
757
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1183
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1184
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2507
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2509
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
735
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
106
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1102
if (pool->psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1103
dmub_psr_destroy(&pool->psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1408
pool->psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1409
if (pool->psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1046
if (pool->psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1047
dmub_psr_destroy(&pool->psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
106
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1340
pool->psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1341
if (pool->psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1484
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1485
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2107
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2108
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
898
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1542
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1543
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
2031
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
2032
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
934
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1484
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1485
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
2055
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
2056
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
896
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1480
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1481
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1931
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1932
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
890
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1490
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1491
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2436
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2437
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1470
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1471
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1931
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1932
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1553
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1554
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2076
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2077
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
792
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1533
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1534
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2048
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2049
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
772
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1534
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1535
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2049
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2050
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
773
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1493
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1494
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2126
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2127
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
614
uint8_t psr;
sys/dev/pci/drm/i915/display/intel_bios.c
1361
panel->vbt.psr.enable = driver->psr_enabled;
sys/dev/pci/drm/i915/display/intel_bios.c
1381
panel->vbt.psr.enable = panel_bool(power->psr, panel_type);
sys/dev/pci/drm/i915/display/intel_bios.c
1556
const struct bdb_psr *psr;
sys/dev/pci/drm/i915/display/intel_bios.c
1560
psr = bdb_find_section(display, BDB_PSR);
sys/dev/pci/drm/i915/display/intel_bios.c
1561
if (!psr) {
sys/dev/pci/drm/i915/display/intel_bios.c
1566
psr_table = &psr->psr_table[panel_type];
sys/dev/pci/drm/i915/display/intel_bios.c
1568
panel->vbt.psr.full_link = psr_table->full_link;
sys/dev/pci/drm/i915/display/intel_bios.c
1569
panel->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
sys/dev/pci/drm/i915/display/intel_bios.c
1570
panel->vbt.psr.idle_frames = psr_table->idle_frames;
sys/dev/pci/drm/i915/display/intel_bios.c
1580
panel->vbt.psr.tp1_wakeup_time_us = 500;
sys/dev/pci/drm/i915/display/intel_bios.c
1583
panel->vbt.psr.tp1_wakeup_time_us = 100;
sys/dev/pci/drm/i915/display/intel_bios.c
1586
panel->vbt.psr.tp1_wakeup_time_us = 0;
sys/dev/pci/drm/i915/display/intel_bios.c
1594
panel->vbt.psr.tp1_wakeup_time_us = 2500;
sys/dev/pci/drm/i915/display/intel_bios.c
1600
panel->vbt.psr.tp2_tp3_wakeup_time_us = 500;
sys/dev/pci/drm/i915/display/intel_bios.c
1603
panel->vbt.psr.tp2_tp3_wakeup_time_us = 100;
sys/dev/pci/drm/i915/display/intel_bios.c
1606
panel->vbt.psr.tp2_tp3_wakeup_time_us = 0;
sys/dev/pci/drm/i915/display/intel_bios.c
1614
panel->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
sys/dev/pci/drm/i915/display/intel_bios.c
1618
panel->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
sys/dev/pci/drm/i915/display/intel_bios.c
1619
panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
sys/dev/pci/drm/i915/display/intel_bios.c
1623
u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
sys/dev/pci/drm/i915/display/intel_bios.c
1641
panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
sys/dev/pci/drm/i915/display/intel_bios.c
1644
panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = panel->vbt.psr.tp2_tp3_wakeup_time_us;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1228
intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_display_types.h
1847
struct intel_psr psr;
sys/dev/pci/drm/i915/display/intel_display_types.h
363
} psr;
sys/dev/pci/drm/i915/display/intel_dp.c
5962
intel_dp->psr.sink_panel_replay_support = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5963
intel_dp->psr.sink_panel_replay_su_support = false;
sys/dev/pci/drm/i915/display/intel_psr.c
1007
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
1008
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1010
if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1011
u32 val = psr->su_region_et_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
1014
if (intel_dp->psr.req_psr2_sdp_prior_scanline)
sys/dev/pci/drm/i915/display/intel_psr.c
1022
PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),
sys/dev/pci/drm/i915/display/intel_psr.c
1025
intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
sys/dev/pci/drm/i915/display/intel_psr.c
1032
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1040
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
1097
if (intel_dp->psr.req_psr2_sdp_prior_scanline)
sys/dev/pci/drm/i915/display/intel_psr.c
1101
psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
sys/dev/pci/drm/i915/display/intel_psr.c
1103
if (intel_dp->psr.psr2_sel_fetch_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1114
if (intel_dp->psr.su_region_et_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1152
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1178
container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
sys/dev/pci/drm/i915/display/intel_psr.c
1180
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1182
if (delayed_work_pending(&intel_dp->psr.dc3co_work))
sys/dev/pci/drm/i915/display/intel_psr.c
1187
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1192
if (!intel_dp->psr.dc3co_exitline)
sys/dev/pci/drm/i915/display/intel_psr.c
1195
cancel_delayed_work(&intel_dp->psr.dc3co_work);
sys/dev/pci/drm/i915/display/intel_psr.c
1267
intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
sys/dev/pci/drm/i915/display/intel_psr.c
1286
if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
sys/dev/pci/drm/i915/display/intel_psr.c
1289
if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
sys/dev/pci/drm/i915/display/intel_psr.c
1294
return intel_dp->psr.su_y_granularity == 4;
sys/dev/pci/drm/i915/display/intel_psr.c
1302
y_granularity = intel_dp->psr.su_y_granularity;
sys/dev/pci/drm/i915/display/intel_psr.c
1303
else if (intel_dp->psr.su_y_granularity <= 2)
sys/dev/pci/drm/i915/display/intel_psr.c
1305
else if ((intel_dp->psr.su_y_granularity % 4) == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
1306
y_granularity = intel_dp->psr.su_y_granularity;
sys/dev/pci/drm/i915/display/intel_psr.c
1456
if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
sys/dev/pci/drm/i915/display/intel_psr.c
1577
!intel_dp->psr.sink_panel_replay_su_support))
sys/dev/pci/drm/i915/display/intel_psr.c
1712
if (intel_dp->psr.sink_not_reliable) {
sys/dev/pci/drm/i915/display/intel_psr.c
1789
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1790
if (!intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1793
if (intel_dp->psr.panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1803
pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;
sys/dev/pci/drm/i915/display/intel_psr.c
1806
if (!intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1816
pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;
sys/dev/pci/drm/i915/display/intel_psr.c
1824
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1830
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1839
drm_WARN_ON(display->drm, intel_dp->psr.active);
sys/dev/pci/drm/i915/display/intel_psr.c
1841
drm_WARN_ON(display->drm, !intel_dp->psr.enabled);
sys/dev/pci/drm/i915/display/intel_psr.c
1843
lockdep_assert_held(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1846
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1848
else if (intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1853
intel_dp->psr.active = true;
sys/dev/pci/drm/i915/display/intel_psr.c
1864
enum pipe pipe = intel_dp->psr.pipe;
sys/dev/pci/drm/i915/display/intel_psr.c
1889
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1953
if (intel_dp->psr.dc3co_exitline)
sys/dev/pci/drm/i915/display/intel_psr.c
1957
intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
sys/dev/pci/drm/i915/display/intel_psr.c
1961
intel_dp->psr.psr2_sel_fetch_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
1970
if (intel_dp->psr.sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1981
if (!intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
1988
if (!intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
2002
!intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2003
intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);
sys/dev/pci/drm/i915/display/intel_psr.c
2011
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2014
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2028
intel_dp->psr.sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
2045
drm_WARN_ON(display->drm, intel_dp->psr.enabled);
sys/dev/pci/drm/i915/display/intel_psr.c
2047
intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
sys/dev/pci/drm/i915/display/intel_psr.c
2048
intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
sys/dev/pci/drm/i915/display/intel_psr.c
2049
intel_dp->psr.busy_frontbuffer_bits = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2050
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
sys/dev/pci/drm/i915/display/intel_psr.c
2051
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2054
intel_dp->psr.dc3co_exit_delay = val;
sys/dev/pci/drm/i915/display/intel_psr.c
2055
intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
sys/dev/pci/drm/i915/display/intel_psr.c
2056
intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
sys/dev/pci/drm/i915/display/intel_psr.c
2057
intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;
sys/dev/pci/drm/i915/display/intel_psr.c
2058
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2059
intel_dp->psr.req_psr2_sdp_prior_scanline =
sys/dev/pci/drm/i915/display/intel_psr.c
2061
intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
2062
intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
sys/dev/pci/drm/i915/display/intel_psr.c
2063
intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;
sys/dev/pci/drm/i915/display/intel_psr.c
2068
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
207
#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
sys/dev/pci/drm/i915/display/intel_psr.c
2072
intel_dp->psr.sel_update_enabled ? "2" : "1");
sys/dev/pci/drm/i915/display/intel_psr.c
208
(intel_dp)->psr.source_support)
sys/dev/pci/drm/i915/display/intel_psr.c
2093
intel_dp->psr.enabled = true;
sys/dev/pci/drm/i915/display/intel_psr.c
2094
intel_dp->psr.pause_counter = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2103
intel_dp->psr.link_ok = true;
sys/dev/pci/drm/i915/display/intel_psr.c
2111
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2114
if (!intel_dp->psr.active) {
sys/dev/pci/drm/i915/display/intel_psr.c
2128
if (intel_dp->psr.panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2129
intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
sys/dev/pci/drm/i915/display/intel_psr.c
2131
} else if (intel_dp->psr.sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2142
intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
2144
intel_dp->psr.pipe,
sys/dev/pci/drm/i915/display/intel_psr.c
2153
intel_dp->psr.active = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2159
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2163
if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
2164
intel_dp->psr.panel_replay_enabled)) {
sys/dev/pci/drm/i915/display/intel_psr.c
2181
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2183
lockdep_assert_held(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2185
if (!intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2188
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2192
intel_dp->psr.sel_update_enabled ? "2" : "1");
sys/dev/pci/drm/i915/display/intel_psr.c
2203
LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0);
sys/dev/pci/drm/i915/display/intel_psr.c
2205
if (intel_dp->psr.sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2207
if (!intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
2220
if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp))
sys/dev/pci/drm/i915/display/intel_psr.c
2224
if (!intel_dp->psr.panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2227
if (intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2235
!intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2236
intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);
sys/dev/pci/drm/i915/display/intel_psr.c
2238
intel_dp->psr.enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2239
intel_dp->psr.panel_replay_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2240
intel_dp->psr.sel_update_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2241
intel_dp->psr.psr2_sel_fetch_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2242
intel_dp->psr.su_region_et_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2243
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2244
intel_dp->psr.active_non_psr_pipes = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2245
intel_dp->psr.pkg_c_latency_used = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2267
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2271
intel_dp->psr.link_ok = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2273
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2274
cancel_work_sync(&intel_dp->psr.work);
sys/dev/pci/drm/i915/display/intel_psr.c
2275
cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
sys/dev/pci/drm/i915/display/intel_psr.c
2286
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
2291
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2293
if (!psr->enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2294
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2298
if (intel_dp->psr.pause_counter++ == 0) {
sys/dev/pci/drm/i915/display/intel_psr.c
2303
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2305
cancel_work_sync(&psr->work);
sys/dev/pci/drm/i915/display/intel_psr.c
2306
cancel_delayed_work_sync(&psr->dc3co_work);
sys/dev/pci/drm/i915/display/intel_psr.c
2318
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
2323
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2325
if (!psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2328
if (!psr->pause_counter) {
sys/dev/pci/drm/i915/display/intel_psr.c
2333
if (--intel_dp->psr.pause_counter == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
2337
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
242
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
sys/dev/pci/drm/i915/display/intel_psr.c
245
connector->panel.vbt.psr.enable : true;
sys/dev/pci/drm/i915/display/intel_psr.c
2492
intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);
sys/dev/pci/drm/i915/display/intel_psr.c
2511
lockdep_assert_held(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2513
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
255
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
sys/dev/pci/drm/i915/display/intel_psr.c
268
return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) &&
sys/dev/pci/drm/i915/display/intel_psr.c
2730
intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
2731
intel_dp->psr.sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
277
EDP_PSR_ERROR(intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
285
EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
293
EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
3007
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3009
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
301
EDP_PSR_MASK(intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
3011
if (psr->enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3023
new_crtc_state->has_sel_update != psr->sel_update_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
3024
new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
3025
new_crtc_state->has_panel_replay != psr->panel_replay_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
3033
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3051
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3054
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3057
psr->enabled && !crtc_state->active_planes);
sys/dev/pci/drm/i915/display/intel_psr.c
3059
keep_disabled |= psr->sink_not_reliable;
sys/dev/pci/drm/i915/display/intel_psr.c
3066
if (!psr->enabled && !keep_disabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3068
else if (psr->enabled && !crtc_state->wm_level_disabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3073
if (crtc_state->crc_enabled && psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3080
intel_dp->psr.busy_frontbuffer_bits = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
3082
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3159
lockdep_assert_held(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3161
if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3164
if (intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3192
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
3197
if (!intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3200
if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
3201
intel_dp->psr.panel_replay_enabled)) {
sys/dev/pci/drm/i915/display/intel_psr.c
3209
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3217
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3218
return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter;
sys/dev/pci/drm/i915/display/intel_psr.c
3301
ret = mutex_lock_interruptible(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3305
old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
sys/dev/pci/drm/i915/display/intel_psr.c
3306
old_disable_bits = intel_dp->psr.debug &
sys/dev/pci/drm/i915/display/intel_psr.c
3310
intel_dp->psr.debug = val;
sys/dev/pci/drm/i915/display/intel_psr.c
3316
if (intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3319
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3329
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3332
psr->sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3340
container_of(work, typeof(*intel_dp), psr.work);
sys/dev/pci/drm/i915/display/intel_psr.c
3342
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3344
if (!intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3347
if (READ_ONCE(intel_dp->psr.irq_aux_error)) {
sys/dev/pci/drm/i915/display/intel_psr.c
3352
if (intel_dp->psr.pause_counter)
sys/dev/pci/drm/i915/display/intel_psr.c
3369
if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
sys/dev/pci/drm/i915/display/intel_psr.c
3374
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3380
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
3382
if (!intel_dp->psr.psr2_sel_fetch_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3401
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3402
if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3403
intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3438
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3439
if (!intel_dp->psr.enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3440
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3445
INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
3446
intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
sys/dev/pci/drm/i915/display/intel_psr.c
3451
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3466
if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
3467
!intel_dp->psr.active)
sys/dev/pci/drm/i915/display/intel_psr.c
3475
INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
sys/dev/pci/drm/i915/display/intel_psr.c
3479
mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
sys/dev/pci/drm/i915/display/intel_psr.c
3480
intel_dp->psr.dc3co_exit_delay);
sys/dev/pci/drm/i915/display/intel_psr.c
3487
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3489
if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3491
if (intel_dp->psr.busy_frontbuffer_bits == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
3492
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
3507
} else if (!intel_dp->psr.psr2_sel_fetch_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3519
if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
sys/dev/pci/drm/i915/display/intel_psr.c
3520
queue_work(display->wq.unordered, &intel_dp->psr.work);
sys/dev/pci/drm/i915/display/intel_psr.c
3545
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3546
if (!intel_dp->psr.enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3547
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3552
INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
3553
intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
sys/dev/pci/drm/i915/display/intel_psr.c
3560
if (intel_dp->psr.pause_counter)
sys/dev/pci/drm/i915/display/intel_psr.c
3565
!intel_dp->psr.psr2_sel_fetch_enabled)) {
sys/dev/pci/drm/i915/display/intel_psr.c
3576
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3614
intel_dp->psr.source_panel_replay_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3617
intel_dp->psr.source_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3622
intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
sys/dev/pci/drm/i915/display/intel_psr.c
3624
INIT_WORK(&intel_dp->psr.work, intel_psr_work);
sys/dev/pci/drm/i915/display/intel_psr.c
3625
INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
sys/dev/pci/drm/i915/display/intel_psr.c
3626
rw_init(&intel_dp->psr.lock, "psrlk");
sys/dev/pci/drm/i915/display/intel_psr.c
3636
offset = intel_dp->psr.panel_replay_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
3643
offset = intel_dp->psr.panel_replay_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
3657
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3659
if (!psr->sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3664
psr->sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3671
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3683
psr->sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3702
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3711
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3713
psr->link_ok = false;
sys/dev/pci/drm/i915/display/intel_psr.c
3715
if (!psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3724
if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) ||
sys/dev/pci/drm/i915/display/intel_psr.c
3727
psr->sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3730
if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR &&
sys/dev/pci/drm/i915/display/intel_psr.c
3751
if (!psr->panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3757
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3767
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3768
ret = intel_dp->psr.enabled;
sys/dev/pci/drm/i915/display/intel_psr.c
3769
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
379
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
3794
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3795
ret = intel_dp->psr.link_ok;
sys/dev/pci/drm/i915/display/intel_psr.c
3796
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
382
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3821
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3844
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3855
if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
386
if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
sys/dev/pci/drm/i915/display/intel_psr.c
3860
if (intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3865
intel_dp->psr.pipe,
sys/dev/pci/drm/i915/display/intel_psr.c
3878
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3880
if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
3881
!intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
3884
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3943
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3945
if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3948
active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
3955
if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes)
sys/dev/pci/drm/i915/display/intel_psr.c
3958
if ((enable && intel_dp->psr.active_non_psr_pipes) ||
sys/dev/pci/drm/i915/display/intel_psr.c
3959
(!enable && !intel_dp->psr.active_non_psr_pipes) ||
sys/dev/pci/drm/i915/display/intel_psr.c
3960
!intel_dp->psr.pkg_c_latency_used) {
sys/dev/pci/drm/i915/display/intel_psr.c
3961
intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
3965
intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
3969
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3989
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3992
intel_dp->psr.vblank_wakeref =
sys/dev/pci/drm/i915/display/intel_psr.c
3997
intel_dp->psr.vblank_wakeref);
sys/dev/pci/drm/i915/display/intel_psr.c
4000
if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
4001
intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
4004
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
4012
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
4017
(intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) {
sys/dev/pci/drm/i915/display/intel_psr.c
4060
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
4063
str_yes_no(psr->sink_support));
sys/dev/pci/drm/i915/display/intel_psr.c
4065
if (psr->sink_support)
sys/dev/pci/drm/i915/display/intel_psr.c
4069
seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
sys/dev/pci/drm/i915/display/intel_psr.c
4071
str_yes_no(psr->sink_panel_replay_su_support));
sys/dev/pci/drm/i915/display/intel_psr.c
4081
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
4084
if (psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4089
if (psr->panel_replay_enabled && psr->sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4091
else if (psr->panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4093
else if (psr->sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4095
else if (psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4100
if (psr->su_region_et_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4111
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
4112
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
4119
if (!(psr->sink_support || psr->sink_panel_replay_support))
sys/dev/pci/drm/i915/display/intel_psr.c
4123
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
4127
if (!psr->enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
4129
str_yes_no(psr->sink_not_reliable));
sys/dev/pci/drm/i915/display/intel_psr.c
4134
if (psr->panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
4143
} else if (psr->sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
4153
if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))
sys/dev/pci/drm/i915/display/intel_psr.c
4158
psr->busy_frontbuffer_bits);
sys/dev/pci/drm/i915/display/intel_psr.c
4167
if (psr->debug & I915_PSR_DEBUG_IRQ) {
sys/dev/pci/drm/i915/display/intel_psr.c
4169
psr->last_entry_attempt);
sys/dev/pci/drm/i915/display/intel_psr.c
4170
seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
sys/dev/pci/drm/i915/display/intel_psr.c
4173
if (psr->sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
4205
str_enabled_disabled(psr->psr2_sel_fetch_enabled));
sys/dev/pci/drm/i915/display/intel_psr.c
4209
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
4273
*val = READ_ONCE(intel_dp->psr.debug);
sys/dev/pci/drm/i915/display/intel_psr.c
4297
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4299
else if (intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
435
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
439
intel_dp->psr.last_entry_attempt = time_ns;
sys/dev/pci/drm/i915/display/intel_psr.c
446
intel_dp->psr.last_exit = time_ns;
sys/dev/pci/drm/i915/display/intel_psr.c
458
psr_event_print(display, val, intel_dp->psr.sel_update_enabled);
sys/dev/pci/drm/i915/display/intel_psr.c
466
intel_dp->psr.irq_aux_error = true;
sys/dev/pci/drm/i915/display/intel_psr.c
479
queue_work(display->wq.unordered, &intel_dp->psr.work);
sys/dev/pci/drm/i915/display/intel_psr.c
501
if (intel_dp->psr.sink_panel_replay_su_support) {
sys/dev/pci/drm/i915/display/intel_psr.c
516
return intel_dp->psr.sink_panel_replay_su_support ?
sys/dev/pci/drm/i915/display/intel_psr.c
524
return intel_dp->psr.sink_panel_replay_su_support ?
sys/dev/pci/drm/i915/display/intel_psr.c
582
intel_dp->psr.su_w_granularity = w;
sys/dev/pci/drm/i915/display/intel_psr.c
583
intel_dp->psr.su_y_granularity = y;
sys/dev/pci/drm/i915/display/intel_psr.c
619
intel_dp->psr.sink_panel_replay_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
623
intel_dp->psr.sink_panel_replay_su_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
627
intel_dp->psr.sink_panel_replay_su_support ?
sys/dev/pci/drm/i915/display/intel_psr.c
659
intel_dp->psr.sink_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
660
intel_dp->psr.sink_sync_latency =
sys/dev/pci/drm/i915/display/intel_psr.c
679
intel_dp->psr.sink_psr2_support = y_req &&
sys/dev/pci/drm/i915/display/intel_psr.c
682
intel_dp->psr.sink_psr2_support ? "" : "not ");
sys/dev/pci/drm/i915/display/intel_psr.c
685
if (intel_dp->psr.sink_psr2_support)
sys/dev/pci/drm/i915/display/intel_psr.c
698
if (intel_dp->psr.sink_psr2_support ||
sys/dev/pci/drm/i915/display/intel_psr.c
699
intel_dp->psr.sink_panel_replay_su_support)
sys/dev/pci/drm/i915/display/intel_psr.c
706
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
745
intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
sys/dev/pci/drm/i915/display/intel_psr.c
789
if (intel_dp->psr.link_standby)
sys/dev/pci/drm/i915/display/intel_psr.c
802
if (intel_dp->psr.entry_setup_frames > 0)
sys/dev/pci/drm/i915/display/intel_psr.c
850
if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
852
else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
sys/dev/pci/drm/i915/display/intel_psr.c
854
else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
sys/dev/pci/drm/i915/display/intel_psr.c
859
if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
861
else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
sys/dev/pci/drm/i915/display/intel_psr.c
863
else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
sys/dev/pci/drm/i915/display/intel_psr.c
873
connector->panel.vbt.psr.tp1_wakeup_time_us == 0 &&
sys/dev/pci/drm/i915/display/intel_psr.c
874
connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
896
idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
sys/dev/pci/drm/i915/display/intel_psr.c
897
idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
sys/dev/pci/drm/i915/display/intel_psr.c
909
struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
914
intel_dp->psr.active_non_psr_pipes ||
sys/dev/pci/drm/i915/display/intel_psr.c
921
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
933
if (intel_dp->psr.link_standby)
sys/dev/pci/drm/i915/display/intel_psr.c
942
val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
sys/dev/pci/drm/i915/display/intel_psr.c
950
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
952
intel_dp->psr.pipe,
sys/dev/pci/drm/i915/display/intel_psr.c
965
if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
sys/dev/pci/drm/i915/display/intel_psr.c
966
connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
sys/dev/pci/drm/i915/display/intel_psr.c
968
else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
sys/dev/pci/drm/i915/display/intel_psr.c
970
else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
sys/dev/pci/drm/i915/display/intel_psr.c
994
intel_dp->psr.sink_sync_latency + 1,
sys/dev/pci/drm/i915/display/intel_psr.c
998
if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)
sys/dev/pci/drm/i915/display/intel_psr.c
999
frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;
sys/dev/pci/drm/i915/display/intel_psr.h
25
#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
sys/dev/pci/drm/i915/display/intel_psr.h
26
(intel_dp)->psr.source_panel_replay_support)
sys/dev/pci/drm/i915/display/intel_vbt_defs.h
1382
u16 psr; /* 228+ */
sys/dev/pci/pccbb.c
1340
u_int32_t psr; /* socket present-state reg */
sys/dev/pci/pccbb.c
1345
psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT);
sys/dev/pci/pccbb.c
1347
if (0x400u & psr) {
sys/dev/pci/pccbb.c
1350
if (0x800u & psr) {