qwx_pcic_read32
soc_hw_version = qwx_pcic_read32(sc, TCSR_SOC_HW_VERSION);
val = qwx_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
val = qwx_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
val = qwx_pcic_read32(sc, PCIE_Q6_COOKIE_ADDR);
val = qwx_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
val = qwx_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
val = qwx_pcic_read32(sc, WLAON_SOC_RESET_CAUSE_REG);
v = qwx_pcic_read32(sc, offset);
v = qwx_pcic_read32(sc, offset);
val = qwx_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
val = qwx_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
val = qwx_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
val = qwx_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
val = qwx_pcic_read32(sc, WLAON_QFPROM_PWR_CTRL_REG);
reg = qwx_pcic_read32(sc, MHI_STATUS);
uint32_t qwx_pcic_read32(struct qwx_softc *, uint32_t);
sc->ops.read32 = qwx_pcic_read32;
qwx_pcic_read32(sc, TCSR_SOC_HW_SUB_VER);