qwx_pci_read
val = qwx_pci_read(sc, offset);
(void) qwx_pci_read(sc, ATH11K_PCI_WINDOW_REG_ADDRESS);
val = qwx_pci_read(sc, window_start +
val = qwx_pci_read(sc, window_start +
psc->bhi_off = qwx_pci_read(sc, MHI_BHI_OFFSET);
psc->bhie_off = qwx_pci_read(sc, MHI_BHIE_OFFSET);
ee = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
state = qwx_pci_read(sc, MHI_STATUS);
state = qwx_pci_read(sc, MHI_STATUS);
ee = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
psc->bhi_off = qwx_pci_read(sc, MHI_BHI_OFFSET);
reg = qwx_pci_read(sc, MHI_CTRL);
reg = qwx_pci_read(sc, MHI_STATUS);
reg = qwx_pci_read(sc, MHI_CTRL);
reg = qwx_pci_read(sc, MHI_CHDBOFF);
reg = qwx_pci_read(sc, MHI_ERDBOFF);
reg = qwx_pci_read(sc, MHI_CFG);
reg = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
reg = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
reg = qwx_pci_read(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS);
reg = qwx_pci_read(sc,
reg = qwx_pci_read(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS);
reg = qwx_pci_read(sc,
uint32_t qwx_pci_read(struct qwx_softc *, uint32_t);
psc->bhi_off = qwx_pci_read(sc, MHI_BHI_OFFSET);
ee = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
state = qwx_pci_read(sc, MHI_STATUS);