sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

102

struct psr_context psr_context = {0};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

127

ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

477

struct psr_context *psr_context)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

479

return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context);

sys/dev/pci/drm/amd/display/dc/dc.h

2409

struct psr_context *psr_context);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

170

struct psr_context *psr_context)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

182

psr_context->psrExitLinkTrainingRequired);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

192

switch (psr_context->controllerId) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

230

psr_context->sdpTransmitLineNumDeadline);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

239

masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

240

masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

242

psr_context->rfb_update_auto_en;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

243

masterCmdData1.bits.dp_port_num = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

244

masterCmdData1.bits.dcp_sel = psr_context->controllerId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

245

masterCmdData1.bits.phy_type = psr_context->phyType;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

247

psr_context->psrFrameCaptureIndicationReq;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

248

masterCmdData1.bits.aux_chan = psr_context->channel;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

249

masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

254

masterCmdData2.bits.dig_fe = psr_context->engineId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

255

masterCmdData2.bits.dig_be = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

257

psr_context->skipPsrWaitForPllLock;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

258

masterCmdData2.bits.frame_delay = psr_context->frame_delay;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

259

masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

261

psr_context->numberOfControllers;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

266

masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

601

struct psr_context *psr_context)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

617

psr_context->psrExitLinkTrainingRequired);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

627

switch (psr_context->controllerId) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

665

psr_context->sdpTransmitLineNumDeadline);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

667

if (psr_context->allow_smu_optimizations)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

677

masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

678

masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

680

psr_context->rfb_update_auto_en;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

681

masterCmdData1.bits.dp_port_num = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

682

masterCmdData1.bits.dcp_sel = psr_context->controllerId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

683

masterCmdData1.bits.phy_type = psr_context->phyType;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

685

psr_context->psrFrameCaptureIndicationReq;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

686

masterCmdData1.bits.aux_chan = psr_context->channel;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

687

masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

688

masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

693

masterCmdData2.bits.dig_fe = psr_context->engineId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

694

masterCmdData2.bits.dig_be = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

696

psr_context->skipPsrWaitForPllLock;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

697

masterCmdData2.bits.frame_delay = psr_context->frame_delay;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

698

masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

700

psr_context->numberOfControllers;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

705

masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

294

struct psr_context *psr_context,

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

324

psr_context->psrExitLinkTrainingRequired);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

328

psr_context->sdpTransmitLineNumDeadline);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

336

copy_settings_data->dpphy_inst = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

337

copy_settings_data->aux_inst = psr_context->channel;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

338

copy_settings_data->digfe_inst = psr_context->engineId;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

339

copy_settings_data->digbe_inst = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

358

copy_settings_data->psr_level = psr_context->psr_level.u32all;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

359

copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

360

copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

361

copy_settings_data->frame_delay = psr_context->frame_delay;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

362

copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

363

copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

370

if (psr_context->su_granularity_required == 0)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

373

copy_settings_data->su_y_granularity = psr_context->su_y_granularity;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

376

copy_settings_data->line_time_in_us = psr_context->line_time_in_us;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

377

copy_settings_data->rate_control_caps = psr_context->rate_control_caps;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

394

copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode || psr_context->os_request_force_ffu;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

425

copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.h

41

struct psr_context *psr_context, uint8_t panel_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h

68

struct psr_context *psr_context);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

276

struct psr_context *psr_context);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

690

struct psr_context *psr_context)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

701

psr_context->controllerId = CONTROLLER_ID_UNDEFINED;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

778

psr_context->su_granularity_required =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

780

psr_context->su_y_granularity =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

782

psr_context->line_time_in_us = psr_config->line_time_in_us;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

788

psr_context->rate_control_caps = psr_config->rate_control_caps;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

795

psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

796

psr_context->transmitterId = link->link_enc->transmitter;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

797

psr_context->engineId = link->link_enc->preferred_engine;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

805

psr_context->controllerId =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

813

psr_context->phyType = PHY_TYPE_UNIPHY;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

815

psr_context->smuPhyId = transmitter_to_phy_id(link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

817

psr_context->crtcTimingVerticalTotal = stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

818

psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

823

psr_context->psrSupportedDisplayConfig = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

824

psr_context->psrExitLinkTrainingRequired =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

826

psr_context->sdpTransmitLineNumDeadline =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

828

psr_context->psrFrameCaptureIndicationReq =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

831

psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

833

psr_context->numberOfControllers =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

836

psr_context->rfb_update_auto_en = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

839

psr_context->timehyst_frames = 2;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

843

psr_context->hyst_lines = stream->timing.v_total / 2 / 100;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

844

psr_context->aux_repeats = 10;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

846

psr_context->psr_level.u32all = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

855

psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

858

psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

868

psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

869

psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

874

psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

877

psr_context->psr_level.bits.DISABLE_ALPM = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

878

psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

883

psr_context->frame_delay = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

885

psr_context->dsc_slice_height = psr_config->dsc_slice_height;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

887

psr_context->os_request_force_ffu = psr_config->os_request_force_ffu;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

891

link, psr_context, panel_inst);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

895

link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

51

struct psr_context *psr_context);