Symbol: psr
sys/arch/arm/include/armreg.h
131
#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
sys/arch/arm64/dev/rtkit.c
332
uint64_t psr;
sys/arch/arm64/dev/rtkit.c
413
printf("RTKit Crg8: psr %016llx\n", rg8.psr);
sys/arch/luna88k/include/cpu.h
22
u_long psr;
sys/arch/luna88k/include/cpu.h
24
psr = get_psr();
sys/arch/luna88k/include/cpu.h
25
set_psr(psr | PSR_IND);
sys/arch/luna88k/include/cpu.h
26
return psr;
sys/arch/luna88k/include/cpu.h
30
intr_restore(u_long psr)
sys/arch/luna88k/include/cpu.h
32
set_psr(psr);
sys/arch/luna88k/luna88k/machdep.c
1196
uint32_t psr;
sys/arch/luna88k/luna88k/machdep.c
1199
psr = get_psr();
sys/arch/luna88k/luna88k/machdep.c
1200
set_psr(psr | PSR_IND);
sys/arch/luna88k/luna88k/machdep.c
1205
set_psr(psr);
sys/arch/luna88k/luna88k/machdep.c
1213
uint32_t psr;
sys/arch/luna88k/luna88k/machdep.c
1216
psr = get_psr();
sys/arch/luna88k/luna88k/machdep.c
1217
set_psr(psr | PSR_IND);
sys/arch/luna88k/luna88k/machdep.c
1223
set_psr(psr);
sys/arch/m88k/include/asm_macro.h
47
set_psr(u_int psr)
sys/arch/m88k/include/asm_macro.h
49
__asm__ volatile ("stcr %0, %%cr1" :: "r" (psr));
sys/arch/m88k/include/asm_macro.h
59
u_int psr;
sys/arch/m88k/include/asm_macro.h
60
__asm__ volatile ("ldcr %0, %%cr1" : "=r" (psr));
sys/arch/m88k/include/asm_macro.h
61
return (psr);
sys/arch/m88k/include/atomic.h
102
u_int psr;
sys/arch/m88k/include/atomic.h
105
psr = get_psr();
sys/arch/m88k/include/atomic.h
106
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
109
set_psr(psr);
sys/arch/m88k/include/atomic.h
34
u_int psr;
sys/arch/m88k/include/atomic.h
36
psr = get_psr();
sys/arch/m88k/include/atomic.h
37
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
39
set_psr(psr);
sys/arch/m88k/include/atomic.h
45
u_int psr;
sys/arch/m88k/include/atomic.h
47
psr = get_psr();
sys/arch/m88k/include/atomic.h
48
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
50
set_psr(psr);
sys/arch/m88k/include/atomic.h
56
u_int psr;
sys/arch/m88k/include/atomic.h
59
psr = get_psr();
sys/arch/m88k/include/atomic.h
60
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
63
set_psr(psr);
sys/arch/m88k/include/atomic.h
71
u_int psr;
sys/arch/m88k/include/atomic.h
74
psr = get_psr();
sys/arch/m88k/include/atomic.h
75
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
78
set_psr(psr);
sys/arch/m88k/include/atomic.h
86
u_int psr;
sys/arch/m88k/include/atomic.h
89
psr = get_psr();
sys/arch/m88k/include/atomic.h
90
set_psr(psr | PSR_IND);
sys/arch/m88k/include/atomic.h
94
set_psr(psr);
sys/arch/m88k/include/cpu.h
115
(uint32_t psr, __cpu_simple_lock_t *lock, uint csr);
sys/arch/m88k/m88k/m88100_machdep.c
351
uint32_t psr;
sys/arch/m88k/m88k/m88100_machdep.c
353
psr = get_psr();
sys/arch/m88k/m88k/m88100_machdep.c
354
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m88100_machdep.c
357
return psr;
sys/arch/m88k/m88k/m88100_machdep.c
361
m88100_mp_atomic_end(uint32_t psr, __cpu_simple_lock_t *lock, uint csr)
sys/arch/m88k/m88k/m88100_machdep.c
364
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
1013
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
1059
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
1060
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
1144
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
752
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
760
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
761
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
765
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
775
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
782
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
783
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
787
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
793
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
800
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
801
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
805
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
811
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
818
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
819
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
823
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
848
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
859
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
860
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
879
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
888
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
899
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
900
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
919
set_psr(psr);
sys/arch/m88k/m88k/m8820x_machdep.c
928
u_int32_t psr;
sys/arch/m88k/m88k/m8820x_machdep.c
939
psr = get_psr();
sys/arch/m88k/m88k/m8820x_machdep.c
940
set_psr(psr | PSR_IND);
sys/arch/m88k/m88k/m8820x_machdep.c
959
set_psr(psr);
sys/arch/m88k/m88k/process_machdep.c
85
unsigned int psr = procregs->epsr;
sys/arch/m88k/m88k/process_machdep.c
89
(psr & PSR_USERSTATIC) | (regs->epsr & ~PSR_USERSTATIC);
sys/arch/m88k/m88k/trap.c
230
u_int psr;
sys/arch/m88k/m88k/trap.c
258
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
260
set_psr(psr);
sys/arch/m88k/m88k/trap.c
265
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
267
set_psr(psr);
sys/arch/m88k/m88k/trap.c
630
u_int psr;
sys/arch/m88k/m88k/trap.c
724
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
726
set_psr(psr);
sys/arch/m88k/m88k/trap.c
731
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
733
set_psr(psr);
sys/arch/m88k/m88k/trap.c
738
set_psr((psr = get_psr()) & ~PSR_IND);
sys/arch/m88k/m88k/trap.c
740
set_psr(psr);
sys/arch/macppc/macppc/cpu.c
124
u_int64_t psr;
sys/arch/macppc/macppc/cpu.c
142
psr = ppc64_mfscomd();
sys/arch/macppc/macppc/cpu.c
144
if (psr & PSR_CMD_COMPLETED)
sys/arch/macppc/macppc/cpu.c
147
} while (psr & PSR_CMD_RECEIVED);
sys/arch/macppc/macppc/cpu.c
149
if ((psr & PSR_FREQ_MASK) == PSR_FREQ_HALF)
sys/arch/macppc/macppc/cpu.c
324
u_int64_t psr;
sys/arch/macppc/macppc/cpu.c
329
psr = ppc64_mfscomd();
sys/arch/macppc/macppc/cpu.c
333
if ((psr & PSR_FREQ_MASK) == PSR_FREQ_HALF) {
sys/dev/acpi/acpiac.c
131
int64_t psr;
sys/dev/acpi/acpiac.c
133
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "_PSR", 0, NULL, &psr)) {
sys/dev/acpi/acpiac.c
138
sc->sc_ac_stat = psr;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9647
struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9656
else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9657
!psr->psr_feature_enabled)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9664
(psr->psr_feature_enabled || pr->config.replay_supported)) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9683
(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9686
if (psr->psr_version == DC_PSR_VERSION_SU_1 &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9687
!psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
312
struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
314
bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
92
if (link->panel_config.psr.disallow_replay)
sys/dev/pci/drm/amd/display/dc/dc.h
269
bool psr;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1222
} psr;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
480
static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
482
psr->ctx = ctx;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
483
psr->funcs = &psr_funcs;
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
491
struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
493
if (psr == NULL) {
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
498
dmub_psr_construct(psr, ctx);
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
500
return psr;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1088
link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
597
link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
628
link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
826
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
277
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
988
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
315
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
575
bool is_psr = link && !link->panel_config.psr.disable_psr &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
357
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
320
struct dmub_psr *psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
589
struct dmub_psr *psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
592
if (psr == NULL && force_static)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
607
if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
608
psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
611
if (psr != NULL && link->psr_settings.psr_feature_enabled &&
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
612
force_static && psr->funcs->psr_force_static)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
613
psr->funcs->psr_force_static(psr, panel_inst);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
622
if (psr != NULL && link->psr_settings.psr_feature_enabled) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
623
psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
637
struct dmub_psr *psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
643
if (psr != NULL && link->psr_settings.psr_feature_enabled)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
644
psr->funcs->psr_get_state(psr, state, panel_inst);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
694
struct dmub_psr *psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
711
if (link->panel_config.psr.read_psrcap_again) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
734
psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
736
if (!dmcu && !psr)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
889
if (psr) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
890
link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
911
struct dmub_psr *psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
918
if (psr != NULL && link->psr_settings.psr_feature_enabled)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
919
psr->funcs->psr_get_residency(psr, residency, panel_inst, mode);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
926
struct dmub_psr *psr = dc->res_pool->psr;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
928
if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
931
psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1532
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1534
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
634
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
756
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
757
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1183
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1184
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2507
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2509
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
735
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
106
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1102
if (pool->psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1103
dmub_psr_destroy(&pool->psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1408
pool->psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1409
if (pool->psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1046
if (pool->psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1047
dmub_psr_destroy(&pool->psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
106
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1340
pool->psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1341
if (pool->psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1484
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1485
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2107
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
2108
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
898
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1542
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1543
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
2031
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
2032
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
934
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1484
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1485
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
2055
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
2056
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
896
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1480
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1481
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1931
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1932
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
890
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1490
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1491
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2436
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2437
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1470
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1471
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1931
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1932
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1553
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1554
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2076
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2077
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
792
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1533
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1534
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2048
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2049
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
772
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1534
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1535
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2049
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2050
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
773
.psr = {
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1493
if (pool->base.psr != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1494
dmub_psr_destroy(&pool->base.psr);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2126
pool->base.psr = dmub_psr_create(ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2127
if (pool->base.psr == NULL) {
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
614
uint8_t psr;
sys/dev/pci/drm/i915/display/intel_bios.c
1361
panel->vbt.psr.enable = driver->psr_enabled;
sys/dev/pci/drm/i915/display/intel_bios.c
1381
panel->vbt.psr.enable = panel_bool(power->psr, panel_type);
sys/dev/pci/drm/i915/display/intel_bios.c
1556
const struct bdb_psr *psr;
sys/dev/pci/drm/i915/display/intel_bios.c
1560
psr = bdb_find_section(display, BDB_PSR);
sys/dev/pci/drm/i915/display/intel_bios.c
1561
if (!psr) {
sys/dev/pci/drm/i915/display/intel_bios.c
1566
psr_table = &psr->psr_table[panel_type];
sys/dev/pci/drm/i915/display/intel_bios.c
1568
panel->vbt.psr.full_link = psr_table->full_link;
sys/dev/pci/drm/i915/display/intel_bios.c
1569
panel->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
sys/dev/pci/drm/i915/display/intel_bios.c
1570
panel->vbt.psr.idle_frames = psr_table->idle_frames;
sys/dev/pci/drm/i915/display/intel_bios.c
1580
panel->vbt.psr.tp1_wakeup_time_us = 500;
sys/dev/pci/drm/i915/display/intel_bios.c
1583
panel->vbt.psr.tp1_wakeup_time_us = 100;
sys/dev/pci/drm/i915/display/intel_bios.c
1586
panel->vbt.psr.tp1_wakeup_time_us = 0;
sys/dev/pci/drm/i915/display/intel_bios.c
1594
panel->vbt.psr.tp1_wakeup_time_us = 2500;
sys/dev/pci/drm/i915/display/intel_bios.c
1600
panel->vbt.psr.tp2_tp3_wakeup_time_us = 500;
sys/dev/pci/drm/i915/display/intel_bios.c
1603
panel->vbt.psr.tp2_tp3_wakeup_time_us = 100;
sys/dev/pci/drm/i915/display/intel_bios.c
1606
panel->vbt.psr.tp2_tp3_wakeup_time_us = 0;
sys/dev/pci/drm/i915/display/intel_bios.c
1614
panel->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
sys/dev/pci/drm/i915/display/intel_bios.c
1618
panel->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
sys/dev/pci/drm/i915/display/intel_bios.c
1619
panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
sys/dev/pci/drm/i915/display/intel_bios.c
1623
u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
sys/dev/pci/drm/i915/display/intel_bios.c
1641
panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
sys/dev/pci/drm/i915/display/intel_bios.c
1644
panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = panel->vbt.psr.tp2_tp3_wakeup_time_us;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1228
intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_display_types.h
1844
struct intel_psr psr;
sys/dev/pci/drm/i915/display/intel_display_types.h
363
} psr;
sys/dev/pci/drm/i915/display/intel_dp.c
5950
intel_dp->psr.sink_panel_replay_support = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5951
intel_dp->psr.sink_panel_replay_su_support = false;
sys/dev/pci/drm/i915/display/intel_psr.c
1000
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1002
if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1003
u32 val = psr->su_region_et_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
1006
if (intel_dp->psr.req_psr2_sdp_prior_scanline)
sys/dev/pci/drm/i915/display/intel_psr.c
1014
PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),
sys/dev/pci/drm/i915/display/intel_psr.c
1017
intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
sys/dev/pci/drm/i915/display/intel_psr.c
1024
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1032
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
1089
if (intel_dp->psr.req_psr2_sdp_prior_scanline)
sys/dev/pci/drm/i915/display/intel_psr.c
1093
psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
sys/dev/pci/drm/i915/display/intel_psr.c
1095
if (intel_dp->psr.psr2_sel_fetch_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1106
if (intel_dp->psr.su_region_et_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1144
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1170
container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
sys/dev/pci/drm/i915/display/intel_psr.c
1172
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1174
if (delayed_work_pending(&intel_dp->psr.dc3co_work))
sys/dev/pci/drm/i915/display/intel_psr.c
1179
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1184
if (!intel_dp->psr.dc3co_exitline)
sys/dev/pci/drm/i915/display/intel_psr.c
1187
cancel_delayed_work(&intel_dp->psr.dc3co_work);
sys/dev/pci/drm/i915/display/intel_psr.c
1259
intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
sys/dev/pci/drm/i915/display/intel_psr.c
1278
if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
sys/dev/pci/drm/i915/display/intel_psr.c
1281
if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
sys/dev/pci/drm/i915/display/intel_psr.c
1286
return intel_dp->psr.su_y_granularity == 4;
sys/dev/pci/drm/i915/display/intel_psr.c
1294
y_granularity = intel_dp->psr.su_y_granularity;
sys/dev/pci/drm/i915/display/intel_psr.c
1295
else if (intel_dp->psr.su_y_granularity <= 2)
sys/dev/pci/drm/i915/display/intel_psr.c
1297
else if ((intel_dp->psr.su_y_granularity % 4) == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
1298
y_granularity = intel_dp->psr.su_y_granularity;
sys/dev/pci/drm/i915/display/intel_psr.c
1423
if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
sys/dev/pci/drm/i915/display/intel_psr.c
1544
!intel_dp->psr.sink_panel_replay_su_support))
sys/dev/pci/drm/i915/display/intel_psr.c
1679
if (intel_dp->psr.sink_not_reliable) {
sys/dev/pci/drm/i915/display/intel_psr.c
1756
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1757
if (!intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1760
if (intel_dp->psr.panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1770
pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;
sys/dev/pci/drm/i915/display/intel_psr.c
1773
if (!intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1783
pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;
sys/dev/pci/drm/i915/display/intel_psr.c
1791
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1797
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1806
drm_WARN_ON(display->drm, intel_dp->psr.active);
sys/dev/pci/drm/i915/display/intel_psr.c
1808
drm_WARN_ON(display->drm, !intel_dp->psr.enabled);
sys/dev/pci/drm/i915/display/intel_psr.c
1810
lockdep_assert_held(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
1813
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1815
else if (intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1820
intel_dp->psr.active = true;
sys/dev/pci/drm/i915/display/intel_psr.c
1831
enum pipe pipe = intel_dp->psr.pipe;
sys/dev/pci/drm/i915/display/intel_psr.c
1856
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1920
if (intel_dp->psr.dc3co_exitline)
sys/dev/pci/drm/i915/display/intel_psr.c
1924
intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
sys/dev/pci/drm/i915/display/intel_psr.c
1928
intel_dp->psr.psr2_sel_fetch_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
1937
if (intel_dp->psr.sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1948
if (!intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
1955
if (!intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
1969
!intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1970
intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);
sys/dev/pci/drm/i915/display/intel_psr.c
1978
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
1981
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1995
intel_dp->psr.sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
2012
drm_WARN_ON(display->drm, intel_dp->psr.enabled);
sys/dev/pci/drm/i915/display/intel_psr.c
2014
intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
sys/dev/pci/drm/i915/display/intel_psr.c
2015
intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
sys/dev/pci/drm/i915/display/intel_psr.c
2016
intel_dp->psr.busy_frontbuffer_bits = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2017
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
sys/dev/pci/drm/i915/display/intel_psr.c
2018
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2021
intel_dp->psr.dc3co_exit_delay = val;
sys/dev/pci/drm/i915/display/intel_psr.c
2022
intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
sys/dev/pci/drm/i915/display/intel_psr.c
2023
intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
sys/dev/pci/drm/i915/display/intel_psr.c
2024
intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;
sys/dev/pci/drm/i915/display/intel_psr.c
2025
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2026
intel_dp->psr.req_psr2_sdp_prior_scanline =
sys/dev/pci/drm/i915/display/intel_psr.c
2028
intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
2029
intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
sys/dev/pci/drm/i915/display/intel_psr.c
2030
intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;
sys/dev/pci/drm/i915/display/intel_psr.c
2035
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2039
intel_dp->psr.sel_update_enabled ? "2" : "1");
sys/dev/pci/drm/i915/display/intel_psr.c
205
#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
sys/dev/pci/drm/i915/display/intel_psr.c
206
(intel_dp)->psr.source_support)
sys/dev/pci/drm/i915/display/intel_psr.c
2060
intel_dp->psr.enabled = true;
sys/dev/pci/drm/i915/display/intel_psr.c
2061
intel_dp->psr.pause_counter = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2070
intel_dp->psr.link_ok = true;
sys/dev/pci/drm/i915/display/intel_psr.c
2078
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2081
if (!intel_dp->psr.active) {
sys/dev/pci/drm/i915/display/intel_psr.c
2095
if (intel_dp->psr.panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2096
intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
sys/dev/pci/drm/i915/display/intel_psr.c
2098
} else if (intel_dp->psr.sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2109
intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
2111
intel_dp->psr.pipe,
sys/dev/pci/drm/i915/display/intel_psr.c
2120
intel_dp->psr.active = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2126
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2130
if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
2131
intel_dp->psr.panel_replay_enabled)) {
sys/dev/pci/drm/i915/display/intel_psr.c
2148
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2150
lockdep_assert_held(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2152
if (!intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2155
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2159
intel_dp->psr.sel_update_enabled ? "2" : "1");
sys/dev/pci/drm/i915/display/intel_psr.c
2170
LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0);
sys/dev/pci/drm/i915/display/intel_psr.c
2172
if (intel_dp->psr.sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2174
if (!intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
2187
if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp))
sys/dev/pci/drm/i915/display/intel_psr.c
2191
if (!intel_dp->psr.panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2194
if (intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2202
!intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2203
intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);
sys/dev/pci/drm/i915/display/intel_psr.c
2205
intel_dp->psr.enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2206
intel_dp->psr.panel_replay_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2207
intel_dp->psr.sel_update_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2208
intel_dp->psr.psr2_sel_fetch_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2209
intel_dp->psr.su_region_et_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2210
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2211
intel_dp->psr.active_non_psr_pipes = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2212
intel_dp->psr.pkg_c_latency_used = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2234
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2238
intel_dp->psr.link_ok = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2240
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2241
cancel_work_sync(&intel_dp->psr.work);
sys/dev/pci/drm/i915/display/intel_psr.c
2242
cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
sys/dev/pci/drm/i915/display/intel_psr.c
2253
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
2258
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2260
if (!psr->enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2261
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2265
if (intel_dp->psr.pause_counter++ == 0) {
sys/dev/pci/drm/i915/display/intel_psr.c
2270
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2272
cancel_work_sync(&psr->work);
sys/dev/pci/drm/i915/display/intel_psr.c
2273
cancel_delayed_work_sync(&psr->dc3co_work);
sys/dev/pci/drm/i915/display/intel_psr.c
2285
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
2290
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2292
if (!psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
2295
if (!psr->pause_counter) {
sys/dev/pci/drm/i915/display/intel_psr.c
2300
if (--intel_dp->psr.pause_counter == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
2304
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
240
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
sys/dev/pci/drm/i915/display/intel_psr.c
243
connector->panel.vbt.psr.enable : true;
sys/dev/pci/drm/i915/display/intel_psr.c
2459
intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);
sys/dev/pci/drm/i915/display/intel_psr.c
2478
lockdep_assert_held(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2480
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
253
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
sys/dev/pci/drm/i915/display/intel_psr.c
266
return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) &&
sys/dev/pci/drm/i915/display/intel_psr.c
2696
intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
2697
intel_dp->psr.sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
275
EDP_PSR_ERROR(intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
283
EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
291
EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
2966
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
2968
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
2970
if (psr->enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
2982
new_crtc_state->has_sel_update != psr->sel_update_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
2983
new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
2984
new_crtc_state->has_panel_replay != psr->panel_replay_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
299
EDP_PSR_MASK(intel_dp->psr.transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
2992
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3010
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3013
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3016
psr->enabled && !crtc_state->active_planes);
sys/dev/pci/drm/i915/display/intel_psr.c
3018
keep_disabled |= psr->sink_not_reliable;
sys/dev/pci/drm/i915/display/intel_psr.c
3025
if (!psr->enabled && !keep_disabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3027
else if (psr->enabled && !crtc_state->wm_level_disabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3032
if (crtc_state->crc_enabled && psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3039
intel_dp->psr.busy_frontbuffer_bits = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
3041
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3118
lockdep_assert_held(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3120
if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3123
if (intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3151
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
3156
if (!intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3159
if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
3160
intel_dp->psr.panel_replay_enabled)) {
sys/dev/pci/drm/i915/display/intel_psr.c
3168
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3176
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3177
return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter;
sys/dev/pci/drm/i915/display/intel_psr.c
3260
ret = mutex_lock_interruptible(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3264
old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
sys/dev/pci/drm/i915/display/intel_psr.c
3265
old_disable_bits = intel_dp->psr.debug &
sys/dev/pci/drm/i915/display/intel_psr.c
3269
intel_dp->psr.debug = val;
sys/dev/pci/drm/i915/display/intel_psr.c
3275
if (intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3278
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3288
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3291
psr->sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3299
container_of(work, typeof(*intel_dp), psr.work);
sys/dev/pci/drm/i915/display/intel_psr.c
3301
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3303
if (!intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3306
if (READ_ONCE(intel_dp->psr.irq_aux_error)) {
sys/dev/pci/drm/i915/display/intel_psr.c
3311
if (intel_dp->psr.pause_counter)
sys/dev/pci/drm/i915/display/intel_psr.c
3328
if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
sys/dev/pci/drm/i915/display/intel_psr.c
3333
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3339
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
3341
if (!intel_dp->psr.psr2_sel_fetch_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3360
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3361
if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3362
intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3397
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3398
if (!intel_dp->psr.enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3399
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3404
INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
3405
intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
sys/dev/pci/drm/i915/display/intel_psr.c
3410
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3425
if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||
sys/dev/pci/drm/i915/display/intel_psr.c
3426
!intel_dp->psr.active)
sys/dev/pci/drm/i915/display/intel_psr.c
3434
INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
sys/dev/pci/drm/i915/display/intel_psr.c
3438
mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
sys/dev/pci/drm/i915/display/intel_psr.c
3439
intel_dp->psr.dc3co_exit_delay);
sys/dev/pci/drm/i915/display/intel_psr.c
3446
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3448
if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3450
if (intel_dp->psr.busy_frontbuffer_bits == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
3451
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
3466
} else if (!intel_dp->psr.psr2_sel_fetch_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3478
if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
sys/dev/pci/drm/i915/display/intel_psr.c
3479
queue_work(display->wq.unordered, &intel_dp->psr.work);
sys/dev/pci/drm/i915/display/intel_psr.c
3504
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3505
if (!intel_dp->psr.enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3506
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3511
INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
3512
intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
sys/dev/pci/drm/i915/display/intel_psr.c
3519
if (intel_dp->psr.pause_counter)
sys/dev/pci/drm/i915/display/intel_psr.c
3524
!intel_dp->psr.psr2_sel_fetch_enabled)) {
sys/dev/pci/drm/i915/display/intel_psr.c
3535
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3573
intel_dp->psr.source_panel_replay_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3576
intel_dp->psr.source_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3581
intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
sys/dev/pci/drm/i915/display/intel_psr.c
3583
INIT_WORK(&intel_dp->psr.work, intel_psr_work);
sys/dev/pci/drm/i915/display/intel_psr.c
3584
INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
sys/dev/pci/drm/i915/display/intel_psr.c
3585
rw_init(&intel_dp->psr.lock, "psrlk");
sys/dev/pci/drm/i915/display/intel_psr.c
3595
offset = intel_dp->psr.panel_replay_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
3602
offset = intel_dp->psr.panel_replay_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
3616
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3618
if (!psr->sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3623
psr->sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3630
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3642
psr->sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3661
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
3670
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3672
psr->link_ok = false;
sys/dev/pci/drm/i915/display/intel_psr.c
3674
if (!psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3683
if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) ||
sys/dev/pci/drm/i915/display/intel_psr.c
3686
psr->sink_not_reliable = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3689
if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR &&
sys/dev/pci/drm/i915/display/intel_psr.c
3710
if (!psr->panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3716
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3726
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3727
ret = intel_dp->psr.enabled;
sys/dev/pci/drm/i915/display/intel_psr.c
3728
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3753
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3754
ret = intel_dp->psr.link_ok;
sys/dev/pci/drm/i915/display/intel_psr.c
3755
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
377
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
3780
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
380
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3803
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3814
if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
3819
if (intel_dp->psr.sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3824
intel_dp->psr.pipe,
sys/dev/pci/drm/i915/display/intel_psr.c
3837
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3839
if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&
sys/dev/pci/drm/i915/display/intel_psr.c
384
if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
sys/dev/pci/drm/i915/display/intel_psr.c
3840
!intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
3843
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3902
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3904
if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3907
active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
3914
if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes)
sys/dev/pci/drm/i915/display/intel_psr.c
3917
if ((enable && intel_dp->psr.active_non_psr_pipes) ||
sys/dev/pci/drm/i915/display/intel_psr.c
3918
(!enable && !intel_dp->psr.active_non_psr_pipes) ||
sys/dev/pci/drm/i915/display/intel_psr.c
3919
!intel_dp->psr.pkg_c_latency_used) {
sys/dev/pci/drm/i915/display/intel_psr.c
3920
intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
3924
intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
3928
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3948
mutex_lock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3949
if (intel_dp->psr.panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
3950
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3954
if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
3957
mutex_unlock(&intel_dp->psr.lock);
sys/dev/pci/drm/i915/display/intel_psr.c
3976
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
3981
(intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) {
sys/dev/pci/drm/i915/display/intel_psr.c
4024
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
4027
str_yes_no(psr->sink_support));
sys/dev/pci/drm/i915/display/intel_psr.c
4029
if (psr->sink_support)
sys/dev/pci/drm/i915/display/intel_psr.c
4033
seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
sys/dev/pci/drm/i915/display/intel_psr.c
4035
str_yes_no(psr->sink_panel_replay_su_support));
sys/dev/pci/drm/i915/display/intel_psr.c
4045
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
4048
if (psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4053
if (psr->panel_replay_enabled && psr->sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4055
else if (psr->panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4057
else if (psr->sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4059
else if (psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4064
if (psr->su_region_et_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4075
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
4076
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.c
4083
if (!(psr->sink_support || psr->sink_panel_replay_support))
sys/dev/pci/drm/i915/display/intel_psr.c
4087
mutex_lock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
4091
if (!psr->enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
4093
str_yes_no(psr->sink_not_reliable));
sys/dev/pci/drm/i915/display/intel_psr.c
4098
if (psr->panel_replay_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
4107
} else if (psr->sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
4117
if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))
sys/dev/pci/drm/i915/display/intel_psr.c
4122
psr->busy_frontbuffer_bits);
sys/dev/pci/drm/i915/display/intel_psr.c
4131
if (psr->debug & I915_PSR_DEBUG_IRQ) {
sys/dev/pci/drm/i915/display/intel_psr.c
4133
psr->last_entry_attempt);
sys/dev/pci/drm/i915/display/intel_psr.c
4134
seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
sys/dev/pci/drm/i915/display/intel_psr.c
4137
if (psr->sel_update_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
4169
str_enabled_disabled(psr->psr2_sel_fetch_enabled));
sys/dev/pci/drm/i915/display/intel_psr.c
4173
mutex_unlock(&psr->lock);
sys/dev/pci/drm/i915/display/intel_psr.c
4237
*val = READ_ONCE(intel_dp->psr.debug);
sys/dev/pci/drm/i915/display/intel_psr.c
4261
if (intel_dp->psr.panel_replay_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4263
else if (intel_dp->psr.enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
433
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
437
intel_dp->psr.last_entry_attempt = time_ns;
sys/dev/pci/drm/i915/display/intel_psr.c
444
intel_dp->psr.last_exit = time_ns;
sys/dev/pci/drm/i915/display/intel_psr.c
456
psr_event_print(display, val, intel_dp->psr.sel_update_enabled);
sys/dev/pci/drm/i915/display/intel_psr.c
464
intel_dp->psr.irq_aux_error = true;
sys/dev/pci/drm/i915/display/intel_psr.c
477
queue_work(display->wq.unordered, &intel_dp->psr.work);
sys/dev/pci/drm/i915/display/intel_psr.c
499
if (intel_dp->psr.sink_panel_replay_su_support) {
sys/dev/pci/drm/i915/display/intel_psr.c
514
return intel_dp->psr.sink_panel_replay_su_support ?
sys/dev/pci/drm/i915/display/intel_psr.c
522
return intel_dp->psr.sink_panel_replay_su_support ?
sys/dev/pci/drm/i915/display/intel_psr.c
580
intel_dp->psr.su_w_granularity = w;
sys/dev/pci/drm/i915/display/intel_psr.c
581
intel_dp->psr.su_y_granularity = y;
sys/dev/pci/drm/i915/display/intel_psr.c
617
intel_dp->psr.sink_panel_replay_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
621
intel_dp->psr.sink_panel_replay_su_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
625
intel_dp->psr.sink_panel_replay_su_support ?
sys/dev/pci/drm/i915/display/intel_psr.c
657
intel_dp->psr.sink_support = true;
sys/dev/pci/drm/i915/display/intel_psr.c
658
intel_dp->psr.sink_sync_latency =
sys/dev/pci/drm/i915/display/intel_psr.c
677
intel_dp->psr.sink_psr2_support = y_req &&
sys/dev/pci/drm/i915/display/intel_psr.c
680
intel_dp->psr.sink_psr2_support ? "" : "not ");
sys/dev/pci/drm/i915/display/intel_psr.c
690
if (intel_dp->psr.sink_psr2_support ||
sys/dev/pci/drm/i915/display/intel_psr.c
691
intel_dp->psr.sink_panel_replay_su_support)
sys/dev/pci/drm/i915/display/intel_psr.c
698
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
737
intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
sys/dev/pci/drm/i915/display/intel_psr.c
781
if (intel_dp->psr.link_standby)
sys/dev/pci/drm/i915/display/intel_psr.c
794
if (intel_dp->psr.entry_setup_frames > 0)
sys/dev/pci/drm/i915/display/intel_psr.c
842
if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
844
else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
sys/dev/pci/drm/i915/display/intel_psr.c
846
else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
sys/dev/pci/drm/i915/display/intel_psr.c
851
if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
853
else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
sys/dev/pci/drm/i915/display/intel_psr.c
855
else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
sys/dev/pci/drm/i915/display/intel_psr.c
865
connector->panel.vbt.psr.tp1_wakeup_time_us == 0 &&
sys/dev/pci/drm/i915/display/intel_psr.c
866
connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
sys/dev/pci/drm/i915/display/intel_psr.c
888
idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
sys/dev/pci/drm/i915/display/intel_psr.c
889
idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
sys/dev/pci/drm/i915/display/intel_psr.c
901
struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
906
intel_dp->psr.active_non_psr_pipes ||
sys/dev/pci/drm/i915/display/intel_psr.c
913
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
925
if (intel_dp->psr.link_standby)
sys/dev/pci/drm/i915/display/intel_psr.c
934
val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
sys/dev/pci/drm/i915/display/intel_psr.c
942
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
sys/dev/pci/drm/i915/display/intel_psr.c
944
intel_dp->psr.pipe,
sys/dev/pci/drm/i915/display/intel_psr.c
957
if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
sys/dev/pci/drm/i915/display/intel_psr.c
958
connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
sys/dev/pci/drm/i915/display/intel_psr.c
960
else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
sys/dev/pci/drm/i915/display/intel_psr.c
962
else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
sys/dev/pci/drm/i915/display/intel_psr.c
986
intel_dp->psr.sink_sync_latency + 1,
sys/dev/pci/drm/i915/display/intel_psr.c
990
if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)
sys/dev/pci/drm/i915/display/intel_psr.c
991
frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;
sys/dev/pci/drm/i915/display/intel_psr.c
999
struct intel_psr *psr = &intel_dp->psr;
sys/dev/pci/drm/i915/display/intel_psr.h
25
#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
sys/dev/pci/drm/i915/display/intel_psr.h
26
(intel_dp)->psr.source_panel_replay_support)
sys/dev/pci/drm/i915/display/intel_vbt_defs.h
1382
u16 psr; /* 228+ */
sys/dev/pci/pccbb.c
1340
u_int32_t psr; /* socket present-state reg */
sys/dev/pci/pccbb.c
1345
psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT);
sys/dev/pci/pccbb.c
1347
if (0x400u & psr) {
sys/dev/pci/pccbb.c
1350
if (0x800u & psr) {