pll_info
info->pll_info.crystal_frequency =
info->pll_info.min_input_pxl_clk_pll_frequency =
info->pll_info.max_input_pxl_clk_pll_frequency =
info->pll_info.min_output_pxl_clk_pll_frequency =
info->pll_info.max_output_pxl_clk_pll_frequency =
info->pll_info.crystal_frequency =
info->pll_info.min_input_pxl_clk_pll_frequency =
info->pll_info.max_input_pxl_clk_pll_frequency =
info->pll_info.min_output_pxl_clk_pll_frequency =
info->pll_info.max_output_pxl_clk_pll_frequency =
info->pll_info.crystal_frequency =
info->pll_info.min_input_pxl_clk_pll_frequency =
info->pll_info.max_input_pxl_clk_pll_frequency =
info->pll_info.min_output_pxl_clk_pll_frequency =
info->pll_info.max_output_pxl_clk_pll_frequency =
info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
if (info->pll_info.crystal_frequency == 0)
info->pll_info.crystal_frequency = 27000;
info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
if (info->pll_info.crystal_frequency == 0) {
info->pll_info.crystal_frequency = 27000;
info->pll_info.crystal_frequency = 100000;
info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;
info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;
info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
const struct audio_pll_info *pll_info,
pll_info->audio_dto_source_clock_in_khz * 10;
const struct audio_pll_info *pll_info)
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
pll_info,
const struct audio_pll_info *pll_info)
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
pll_info,
const struct audio_pll_info *pll_info);
calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
fw_info->pll_info.min_output_pxl_clk_pll_frequency;
fw_info->pll_info.max_output_pxl_clk_pll_frequency;
fw_info->pll_info.max_input_pxl_clk_pll_frequency;
fw_info->pll_info.min_input_pxl_clk_pll_frequency;
clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;
dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;
dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;
audio_output->pll_info.audio_dto_source_clock_in_khz =
audio_output->pll_info.dto_source =
audio_output->pll_info.ss_enabled = true;
audio_output->pll_info.ss_percentage =
&audio_output.pll_info);
&audio_output.pll_info);
&audio_output.pll_info);
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
const struct audio_pll_info *pll_info);
soc_bb->xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000;
struct audio_pll_info pll_info;
} pll_info;
uint16_t pll_info;
pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
if (pll_info) {
rev = RBIOS8(pll_info);
p1pll->reference_freq = RBIOS16(pll_info + 0xe);
p1pll->reference_div = RBIOS16(pll_info + 0x10);
p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
spll->reference_freq = RBIOS16(pll_info + 0x1a);
spll->reference_div = RBIOS16(pll_info + 0x1c);
spll->pll_out_min = RBIOS32(pll_info + 0x1e);
spll->pll_out_max = RBIOS32(pll_info + 0x22);
spll->pll_in_min = RBIOS32(pll_info + 0x48);
spll->pll_in_max = RBIOS32(pll_info + 0x4c);
mpll->reference_freq = RBIOS16(pll_info + 0x26);
mpll->reference_div = RBIOS16(pll_info + 0x28);
mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
sclk = RBIOS16(pll_info + 0xa);
mclk = RBIOS16(pll_info + 0x8);
if (RBIOS32(pll_info + 0x16))
rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);