games/atc/struct.h

77

struct plane *next, *prev;

lib/libexpat/lib/xmltok.c

632

int plane; \

lib/libexpat/lib/xmltok.c

683

plane = (((hi & 0x3) << 2) | ((lo >> 6) & 0x3)) + 1; \

lib/libexpat/lib/xmltok.c

684

*(*toP)++ = (char)((plane >> 2) | UTF8_cval4); \

lib/libexpat/lib/xmltok.c

685

*(*toP)++ = (((lo >> 2) & 0xF) | ((plane & 0x3) << 4) | 0x80); \

sys/dev/fdt/rkvop.c

260

rkvop_plane_check(struct drm_plane *plane, struct drm_atomic_state *das)

sys/dev/fdt/rkvop.c

264

plane);

sys/dev/fdt/rkvop.c

279

rkvop_plane_update(struct drm_plane *plane, struct drm_atomic_state *das)

sys/dev/fdt/rkvop.c

281

struct drm_plane_state *state = plane->state;

sys/dev/fdt/rkvop.c

523

struct drm_plane *plane = &sc->sc_plane;

sys/dev/fdt/rkvop.c

531

drm_plane_helper_add(plane, &rkvop_plane_helper_funcs);

sys/dev/fdt/rkvop.c

532

error = drm_universal_plane_init(ddev, plane, 0, &rkvop_plane_funcs,

sys/dev/fdt/rkvop.c

538

error = drm_crtc_init_with_planes(ddev, crtc, plane, NULL,

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1008

static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1014

((plane && plane < format->num_planes) ? format->hsub : 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1016

((plane && plane < format->num_planes) ? format->vsub : 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1017

unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1023

if (rfb->base.pitches[plane] % block_pitch) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1026

rfb->base.pitches[plane], plane, block_pitch);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1029

if (rfb->base.pitches[plane] < min_pitch) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1032

rfb->base.pitches[plane], plane, min_pitch);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1037

if (rfb->base.offsets[plane] % block_size) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1040

rfb->base.offsets[plane], plane, block_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1044

size = rfb->base.offsets[plane] +

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1045

(uint64_t)rfb->base.pitches[plane] / block_pitch *

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1051

rfb->base.obj[0]->size, size, plane);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1823

int amdgpu_display_get_scanout_buffer(struct drm_plane *plane,

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1829

if (drm_drv_uses_atomic_modeset(plane->dev))

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1830

fb = plane->state->fb;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1832

fb = plane->fb;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1854

drm_warn(plane->dev, "amdgpu panic, framebuffer not in VRAM\n");

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1859

drm_warn(plane->dev, "amdgpu panic, pixel format is not 32bits\n");

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1868

drm_warn(plane->dev, "amdgpu bo map failed, panic won't be displayed\n");

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

55

int amdgpu_display_get_scanout_buffer(struct drm_plane *plane,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2684

static void dce_v10_0_panic_flush(struct drm_plane *plane)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2691

if (!plane->fb)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2694

fb = plane->fb;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2695

amdgpu_crtc = to_amdgpu_crtc(plane->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2651

static void dce_v6_0_panic_flush(struct drm_plane *plane)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2658

if (!plane->fb)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2661

fb = plane->fb;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2662

amdgpu_crtc = to_amdgpu_crtc(plane->crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2610

static void dce_v8_0_panic_flush(struct drm_plane *plane)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2617

if (!plane->fb)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2620

fb = plane->fb;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2621

amdgpu_crtc = to_amdgpu_crtc(plane->crtc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10985

struct drm_plane *plane = disconnected_acrtc->base.primary;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11021

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11503

struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11511

struct amdgpu_device *adev = drm_to_adev(plane->dev);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11558

if (plane->type == DRM_PLANE_TYPE_CURSOR &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11731

struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11740

drm_atomic_plane_disabling(plane->state, new_plane_state))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11791

struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11818

if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11819

ret = dm_check_native_cursor_state(new_plane_crtc, plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11827

needs_reset = should_reset_plane(state, plane, old_plane_state,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11846

plane->base.id, old_plane_crtc->base.id);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11871

if (drm_atomic_plane_disabling(plane->state, new_plane_state))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11899

plane->base.id, new_plane_crtc->base.id);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11937

dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11949

if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11950

ret = dm_check_native_cursor_state(new_plane_crtc, plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12004

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12012

for_each_new_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12016

plane->base.id >= prev_id))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12022

plane->base.id > highest_id)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12024

highest_id = plane->base.id;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12040

#define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12043

for_each_if(((plane) = __i->ptr, \

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12044

(void)(plane) /* Only to avoid unused-but-set-variable warning */, \

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12121

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12145

for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12149

if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12152

if (plane->type == DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12195

for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12198

if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12199

plane->type == DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12244

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12247

drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12248

new_plane_state = drm_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12249

old_plane_state = drm_atomic_get_old_plane_state(state, plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12297

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12395

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12396

if (plane->type == DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12409

drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12410

if (plane->type == DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12414

drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12469

for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12471

ret = dm_update_plane_state(dc, state, plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12510

for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12511

ret = dm_update_plane_state(dc, state, plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3192

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3221

for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5274

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5278

plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5279

if (!plane) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5283

plane->type = plane_type;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5295

ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5299

kfree(plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5304

mode_info->planes[plane_id] = plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5354

const struct dc_plane_cap *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5383

plane = &dm->dc->caps.planes[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5386

DRM_PLANE_TYPE_PRIMARY, plane)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5402

struct dc_plane_cap *plane = &dm->dc->caps.planes[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5408

if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5411

if (!plane->pixel_format_support.argb8888)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5418

DRM_PLANE_TYPE_OVERLAY, plane)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6195

static inline void fill_dc_dirty_rect(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6208

drm_dbg(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6210

plane->base.id, width, height);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6212

drm_dbg(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6214

plane->base.id, x, y, width, height);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6245

static void fill_dc_dirty_rects(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6266

if (plane->type == DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6286

fill_dc_dirty_rect(new_plane_state->plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6309

drm_dbg(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6311

new_plane_state->plane->base.id,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6320

fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6327

fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6336

fill_dc_dirty_rect(new_plane_state->plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6341

fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6352

fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9556

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9564

for_each_old_plane_in_state(state, plane, old_plane_state, i)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9565

if (plane->type == DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9566

amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9576

static void amdgpu_dm_update_cursor(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9580

struct amdgpu_device *adev = drm_to_adev(plane->dev);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9581

struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9582

struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9590

if (!plane->state->fb && !old_plane_state->fb)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9593

drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n",

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9594

amdgpu_crtc->crtc_id, plane->state->crtc_w,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9595

plane->state->crtc_h);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9597

ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9611

amdgpu_crtc->cursor_width = plane->state->crtc_w;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9612

amdgpu_crtc->cursor_height = plane->state->crtc_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9617

attributes.width = plane->state->crtc_w;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9618

attributes.height = plane->state->crtc_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9708

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9765

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9775

if (plane->type == DRM_PLANE_TYPE_CURSOR &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9781

amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9832

new_plane_state->plane->index,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9840

fill_dc_dirty_rects(plane, old_plane_state,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9881

plane->base.id, plane->name);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9901

if (plane == pcrtc->primary)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1205

drm_dbg_kms(plane_state->plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1207

plane_state->plane->index);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1220

drm_dbg_kms(plane_state->plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1222

plane_state->plane->index);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

624

struct drm_plane *plane;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

627

drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

631

if (plane->type == DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

634

new_plane_state = drm_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

746

struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

768

plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h

47

struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1024

static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1103

if (state->plane->type != DRM_PLANE_TYPE_CURSOR) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1201

if (state->plane && state->plane->dev && state->fb) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1202

amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->plane->dev, state->fb,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1229

static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1233

plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1234

struct amdgpu_device *adev = drm_to_adev(plane->dev);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1268

static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1276

if (plane->type != DRM_PLANE_TYPE_OVERLAY)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1278

} else if (plane->type != DRM_PLANE_TYPE_CURSOR) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1282

new_plane_state = drm_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1292

int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1296

struct amdgpu_device *adev = drm_to_adev(plane->dev);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1300

if (!crtc || !plane->state->fb)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1303

if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1304

(plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1307

plane->state->crtc_w,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1308

plane->state->crtc_h);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1312

x = plane->state->crtc_x;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1313

y = plane->state->crtc_y;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1339

void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1342

struct amdgpu_device *adev = drm_to_adev(plane->dev);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1343

struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1344

struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1352

if (!plane->state->fb && !old_plane_state->fb)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1355

drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n",

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1356

amdgpu_crtc->crtc_id, plane->state->crtc_w,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1357

plane->state->crtc_h);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1359

ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1374

amdgpu_crtc->cursor_width = plane->state->crtc_w;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1375

amdgpu_crtc->cursor_height = plane->state->crtc_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1380

attributes.width = plane->state->crtc_w;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1381

attributes.height = plane->state->crtc_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1409

static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1413

plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1415

drm_atomic_get_old_plane_state(state, plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1419

swap(plane->state->fb, new_state->fb);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1421

plane->state->src_x = new_state->src_x;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1422

plane->state->src_y = new_state->src_y;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1423

plane->state->src_w = new_state->src_w;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1424

plane->state->src_h = new_state->src_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1425

plane->state->crtc_x = new_state->crtc_x;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1426

plane->state->crtc_y = new_state->crtc_y;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1427

plane->state->crtc_w = new_state->crtc_w;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1428

plane->state->crtc_h = new_state->crtc_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1430

amdgpu_dm_plane_handle_cursor_update(plane, old_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1433

static void amdgpu_dm_plane_panic_flush(struct drm_plane *plane)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1435

struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane->state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1436

struct drm_framebuffer *fb = plane->state->fb;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1465

static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1469

if (plane->state)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1470

plane->funcs->atomic_destroy_state(plane, plane->state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1478

__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1485

static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1489

old_dm_plane_state = to_dm_plane_state(plane->state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1494

__drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1525

static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1529

struct amdgpu_device *adev = drm_to_adev(plane->dev);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1547

for (i = 0; i < plane->modifier_count; i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1548

if (modifier == plane->modifiers[i])

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1551

if (i == plane->modifier_count)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1587

static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1606

drm_atomic_helper_plane_destroy_state(plane, state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1612

struct drm_plane *plane)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1621

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1624

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1627

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1632

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1638

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1642

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1644

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1647

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1650

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1652

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1658

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1660

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1663

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1670

dm_atomic_plane_set_property(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1676

struct amdgpu_device *adev = drm_to_adev(plane->dev);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1681

ret = drm_property_replace_blob_from_id(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1699

ret = drm_property_replace_blob_from_id(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1707

ret = drm_property_replace_blob_from_id(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1720

ret = drm_property_replace_blob_from_id(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1728

ret = drm_property_replace_blob_from_id(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1741

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1743

plane->base.id, plane->name,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1752

dm_atomic_plane_get_property(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1758

struct amdgpu_device *adev = drm_to_adev(plane->dev);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1807

struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1818

num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1821

res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1828

res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1830

modifiers, plane->type, NULL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1835

if (plane->type == DRM_PLANE_TYPE_OVERLAY &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1841

drm_plane_create_alpha_property(plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1842

drm_plane_create_blend_mode_property(plane, blend_caps);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1845

if (plane->type == DRM_PLANE_TYPE_PRIMARY) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1850

drm_plane_create_zpos_immutable_property(plane, primary_zpos);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1851

} else if (plane->type == DRM_PLANE_TYPE_OVERLAY) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1856

unsigned int zpos = primary_zpos + 1 + drm_plane_index(plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1858

drm_plane_create_zpos_property(plane, zpos, 0, 254);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1859

} else if (plane->type == DRM_PLANE_TYPE_CURSOR) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1860

drm_plane_create_zpos_immutable_property(plane, 255);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1863

if (plane->type == DRM_PLANE_TYPE_PRIMARY &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1869

plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1883

plane->type != DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1884

drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1888

plane->type != DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1889

drm_plane_enable_fb_damage_clips(plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1891

if (plane->type == DRM_PLANE_TYPE_PRIMARY)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1892

drm_plane_helper_add(plane, &dm_primary_plane_helper_funcs);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1894

drm_plane_helper_add(plane, &dm_plane_helper_funcs);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1897

dm_atomic_plane_attach_color_mgmt_properties(dm, plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1900

if (plane->funcs->reset)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1901

plane->funcs->reset(plane);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

779

static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

791

if (plane->type == DRM_PLANE_TYPE_PRIMARY ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

792

(plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURSOR)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

811

switch (plane->type) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

924

static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

961

if (plane->type != DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

980

r = drm_gem_plane_helper_prepare_fb(plane, new_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

998

dm_plane_state_old = to_dm_plane_state(plane->state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

32

int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

35

void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

57

struct drm_plane *plane,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

258

__entry->plane_id = state->plane->base.id;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

259

__entry->plane_type = state->plane->type;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

732

struct dc_plane_state *plane = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

741

if (!plane || !stream)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

754

plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

893

plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2010

int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2019

if (pipe->plane_state == plane && pipe->prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2021

pipe->top_pipe->plane_state != plane)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2033

while (pipe && pipe->plane_state == plane) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2505

const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2515

if (pipe->plane_state == plane)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3378

const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3387

dpp_pipe_count = resource_get_dpp_pipes_for_plane(plane,

sys/dev/pci/drm/amd/display/dc/dc.h

1938

uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1119

struct dc_plane_state *plane;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1146

struct pipe_ctx *dpp_pipe, struct dc_plane_state *plane, int diff)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1152

if (table->mpc_combines[i].plane == plane &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1161

table->mpc_combines[i].plane = plane;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1281

table->mpc_combines[i].plane,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10204

dml_print("DML::%s: pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, pipe_idx, mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[plane_idx]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10205

return (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[plane_idx] == dml_use_mall_pstate_change_phantom_pipe);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6230

CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(mode_lib->ms.SwathWidthYThisState[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6233

CalculatePrefetchSchedule_params->GPUVMPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6234

CalculatePrefetchSchedule_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6235

CalculatePrefetchSchedule_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6236

CalculatePrefetchSchedule_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6238

CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6240

CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6241

CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6313

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6319

if (mode_lib->ms.cache_display_cfg.plane.GPUVMEnable && mode_lib->ms.cache_display_cfg.plane.HostVMEnable)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6331

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6332

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6338

mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6356

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6370

myPipe->ScalerEnabled = mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6371

myPipe->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6377

myPipe->NumberOfCursors = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6420

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6428

mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6429

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6442

mode_lib->ms.cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] *

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6443

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6451

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6546

mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6547

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6548

mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6549

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6558

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6559

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6578

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6649

CalculateWatermarks_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6671

CalculateWatermarks_params->LBBitPerPixel = mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6674

CalculateWatermarks_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6675

CalculateWatermarks_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6676

CalculateWatermarks_params->VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6677

CalculateWatermarks_params->VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6678

CalculateWatermarks_params->VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6679

CalculateWatermarks_params->VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6684

CalculateWatermarks_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6748

if (mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k] == false

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6756

|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] != 1.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6757

|| mode_lib->ms.cache_display_cfg.plane.HTaps[k] != 1.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6758

|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] != 1.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6759

|| mode_lib->ms.cache_display_cfg.plane.VTaps[k] != 1.0)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6761

} else if (mode_lib->ms.cache_display_cfg.plane.VTaps[k] < 1.0 || mode_lib->ms.cache_display_cfg.plane.VTaps[k] > 8.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6762

|| mode_lib->ms.cache_display_cfg.plane.HTaps[k] < 1.0 || mode_lib->ms.cache_display_cfg.plane.HTaps[k] > 8.0

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6763

|| (mode_lib->ms.cache_display_cfg.plane.HTaps[k] > 1.0 && (mode_lib->ms.cache_display_cfg.plane.HTaps[k] % 2) == 1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6764

|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] > mode_lib->ms.ip.max_hscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6765

|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] > mode_lib->ms.ip.max_vscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6766

|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] > mode_lib->ms.cache_display_cfg.plane.HTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6767

|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] > mode_lib->ms.cache_display_cfg.plane.VTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6774

&& (mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k] < 1 || mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k] > 8 || mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] < 1 || mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] > 8 ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6775

(mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] > 1 && mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] % 2 == 1) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6776

mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k] > mode_lib->ms.ip.max_hscl_ratio ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6777

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k] > mode_lib->ms.ip.max_vscl_ratio ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6778

mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k] > mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6779

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k] > mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k]))) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6787

if (mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear && (!(!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) || mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6814

if (!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6815

mode_lib->ms.SwathWidthYSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportWidth[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6816

mode_lib->ms.SwathWidthCSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6818

mode_lib->ms.SwathWidthYSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6819

mode_lib->ms.SwathWidthCSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6823

mode_lib->ms.ReadBandwidthLuma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * dml_ceil(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6824

mode_lib->ms.ReadBandwidthChroma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * dml_ceil(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k] / 2.0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6890

mode_lib->ms.cache_display_cfg.plane.HRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6891

mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6892

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6893

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6898

mode_lib->ms.cache_display_cfg.plane.HTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6899

mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6900

mode_lib->ms.cache_display_cfg.plane.VTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6901

mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6911

} else if (!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelC[k] > 0 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6913

} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelC[k] > 0 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6917

} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelY[k] == 8 && mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6928

mode_lib->ms.MaximumSwathWidthInLineBufferLuma = mode_lib->ms.ip.line_buffer_size_bits * dml_max(mode_lib->ms.cache_display_cfg.plane.HRatio[k], 1.0) / mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6929

(mode_lib->ms.cache_display_cfg.plane.VTaps[k] + dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatio[k], 1.0) - 2, 0.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6935

* dml_max(mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k], 1.0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6936

/ mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6937

/ (mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6938

+ dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k], 1.0) - 2, 0.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6946

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6968

CalculateSwathAndDETConfiguration_params->DETSizeOverride = mode_lib->ms.cache_display_cfg.plane.DETSizeOverride;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6969

CalculateSwathAndDETConfiguration_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6986

CalculateSwathAndDETConfiguration_params->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6987

CalculateSwathAndDETConfiguration_params->ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6990

CalculateSwathAndDETConfiguration_params->ViewportWidth = mode_lib->ms.cache_display_cfg.plane.ViewportWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6991

CalculateSwathAndDETConfiguration_params->ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6992

CalculateSwathAndDETConfiguration_params->ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6993

CalculateSwathAndDETConfiguration_params->ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6994

CalculateSwathAndDETConfiguration_params->ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6995

CalculateSwathAndDETConfiguration_params->ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7005

CalculateSwathAndDETConfiguration_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7011

CalculateSwathAndDETConfiguration_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7012

CalculateSwathAndDETConfiguration_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7099

(mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k),

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7256

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7303

mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7320

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7367

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7386

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1 && mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7389

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1 && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7397

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7491

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m && mode_lib->ms.RequiresDSC[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7507

CalculateSwathAndDETConfiguration_params->DETSizeOverride = mode_lib->ms.cache_display_cfg.plane.DETSizeOverride;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7508

CalculateSwathAndDETConfiguration_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7525

CalculateSwathAndDETConfiguration_params->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7526

CalculateSwathAndDETConfiguration_params->ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7529

CalculateSwathAndDETConfiguration_params->ViewportWidth = mode_lib->ms.cache_display_cfg.plane.ViewportWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7530

CalculateSwathAndDETConfiguration_params->ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7531

CalculateSwathAndDETConfiguration_params->ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7532

CalculateSwathAndDETConfiguration_params->ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7533

CalculateSwathAndDETConfiguration_params->ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7534

CalculateSwathAndDETConfiguration_params->ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7544

CalculateSwathAndDETConfiguration_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7550

CalculateSwathAndDETConfiguration_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7551

CalculateSwathAndDETConfiguration_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7588

mode_lib->ms.cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7594

mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7596

mode_lib->ms.cache_display_cfg.plane.ViewportStationary,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7597

mode_lib->ms.cache_display_cfg.plane.ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7598

mode_lib->ms.cache_display_cfg.plane.ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7599

mode_lib->ms.cache_display_cfg.plane.ViewportXStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7600

mode_lib->ms.cache_display_cfg.plane.ViewportYStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7601

mode_lib->ms.cache_display_cfg.plane.ViewportWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7602

mode_lib->ms.cache_display_cfg.plane.ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7604

mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7605

mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7649

s->SurfParameters[k].SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7650

s->SurfParameters[k].ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7651

s->SurfParameters[k].ViewportHeightChroma = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7668

s->SurfParameters[k].VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7669

s->SurfParameters[k].VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7670

s->SurfParameters[k].VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7671

s->SurfParameters[k].VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7676

s->SurfParameters[k].ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7677

s->SurfParameters[k].ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7678

s->SurfParameters[k].ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7679

s->SurfParameters[k].ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7680

s->SurfParameters[k].ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7681

s->SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->ms.cache_display_cfg.plane.ForceOneRowForFrame[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7692

CalculateVMRowAndSwath_params->UseMALLForStaticScreen = mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7693

CalculateVMRowAndSwath_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7697

CalculateVMRowAndSwath_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7698

CalculateVMRowAndSwath_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7699

CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7700

CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7701

CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7703

CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7704

CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7797

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7805

mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7806

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7807

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7808

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7824

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7825

mode_lib->ms.cache_display_cfg.plane.VRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7829

mode_lib->ms.cache_display_cfg.plane.HRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7830

mode_lib->ms.cache_display_cfg.plane.HRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7846

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7861

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[m] == k && mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7878

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7925

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe || ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == true || mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7926

(mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame || mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7932

((mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_enable || mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_optimize) && (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe)) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7933

((mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_disable || mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_optimize) && (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7941

if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7943

if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7948

if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7955

UseMinimumDCFCLK_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7968

UseMinimumDCFCLK_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7969

UseMinimumDCFCLK_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7970

UseMinimumDCFCLK_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7973

UseMinimumDCFCLK_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7981

UseMinimumDCFCLK_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7982

UseMinimumDCFCLK_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8004

UseMinimumDCFCLK_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8017

mode_lib->ms.cache_display_cfg.plane.HostVMEnable, mode_lib->ms.DCFCLKState[j], mode_lib->ms.state.fabricclk_mhz,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8020

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8045

((mode_lib->ms.state.use_ideal_dram_bw_strobe && !mode_lib->ms.cache_display_cfg.plane.HostVMEnable) ?

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8064

if (mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] > 0.0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8065

if (mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] == 64 && mode_lib->ms.ip.cursor_64bpp_support == false) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8106

if (mode_lib->ms.cache_display_cfg.plane.ViewportWidth[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k] || mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8110

if (mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k] || mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8179

&& ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !s->ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8245

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8282

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8363

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8385

mode_lib->ms.cache_display_cfg.plane.HRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8386

mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8387

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8388

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8393

mode_lib->ms.cache_display_cfg.plane.HTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8394

mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8395

mode_lib->ms.cache_display_cfg.plane.VTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8396

mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8451

mode_lib->ms.cache_display_cfg.plane.SourceScan,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8452

mode_lib->ms.cache_display_cfg.plane.ViewportStationary,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8453

mode_lib->ms.cache_display_cfg.plane.ViewportWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8454

mode_lib->ms.cache_display_cfg.plane.ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8455

mode_lib->ms.cache_display_cfg.plane.ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8456

mode_lib->ms.cache_display_cfg.plane.ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8457

mode_lib->ms.cache_display_cfg.plane.ViewportXStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8458

mode_lib->ms.cache_display_cfg.plane.ViewportYStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8470

mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8472

mode_lib->ms.cache_display_cfg.plane.HRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8486

locals->ReadBandwidthSurfaceLuma[k] = locals->SwathWidthSingleDPPY[k] * locals->BytePerPixelY[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8487

locals->ReadBandwidthSurfaceChroma[k] = locals->SwathWidthSingleDPPC[k] * locals->BytePerPixelC[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8492

CalculateSwathAndDETConfiguration_params->DETSizeOverride = mode_lib->ms.cache_display_cfg.plane.DETSizeOverride;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8493

CalculateSwathAndDETConfiguration_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8510

CalculateSwathAndDETConfiguration_params->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8511

CalculateSwathAndDETConfiguration_params->ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8514

CalculateSwathAndDETConfiguration_params->ViewportWidth = mode_lib->ms.cache_display_cfg.plane.ViewportWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8515

CalculateSwathAndDETConfiguration_params->ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8516

CalculateSwathAndDETConfiguration_params->ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8517

CalculateSwathAndDETConfiguration_params->ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8518

CalculateSwathAndDETConfiguration_params->ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8519

CalculateSwathAndDETConfiguration_params->ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8529

CalculateSwathAndDETConfiguration_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8535

CalculateSwathAndDETConfiguration_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8536

CalculateSwathAndDETConfiguration_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8564

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8565

mode_lib->ms.cache_display_cfg.plane.VRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8569

mode_lib->ms.cache_display_cfg.plane.HRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8570

mode_lib->ms.cache_display_cfg.plane.HRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8584

if ((mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] != k) || !mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8621

if (j != k && mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j && mode_lib->ms.cache_display_cfg.hw.DSCEnabled[j])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8628

mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8630

mode_lib->ms.cache_display_cfg.plane.ViewportStationary,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8631

mode_lib->ms.cache_display_cfg.plane.ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8632

mode_lib->ms.cache_display_cfg.plane.ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8633

mode_lib->ms.cache_display_cfg.plane.ViewportXStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8634

mode_lib->ms.cache_display_cfg.plane.ViewportYStartC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8635

mode_lib->ms.cache_display_cfg.plane.ViewportWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8636

mode_lib->ms.cache_display_cfg.plane.ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8638

mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8639

mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8661

s->SurfaceParameters[k].SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8662

s->SurfaceParameters[k].ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8663

s->SurfaceParameters[k].ViewportHeightChroma = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8680

s->SurfaceParameters[k].VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8681

s->SurfaceParameters[k].VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8682

s->SurfaceParameters[k].VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8683

s->SurfaceParameters[k].VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8688

s->SurfaceParameters[k].ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8689

s->SurfaceParameters[k].ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8690

s->SurfaceParameters[k].ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8691

s->SurfaceParameters[k].ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8692

s->SurfaceParameters[k].ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8693

s->SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->ms.cache_display_cfg.plane.ForceOneRowForFrame[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8704

CalculateVMRowAndSwath_params->UseMALLForStaticScreen = mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8705

CalculateVMRowAndSwath_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8709

CalculateVMRowAndSwath_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8710

CalculateVMRowAndSwath_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8711

CalculateVMRowAndSwath_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8712

CalculateVMRowAndSwath_params->GPUVMMaxPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8713

CalculateVMRowAndSwath_params->GPUVMMinPageSizeKBytes = mode_lib->ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8715

CalculateVMRowAndSwath_params->PTEBufferModeOverrideEn = mode_lib->ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8716

CalculateVMRowAndSwath_params->PTEBufferModeOverrideVal = mode_lib->ms.cache_display_cfg.plane.PTEBufferMode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8772

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8794

if (mode_lib->ms.cache_display_cfg.plane.GPUVMEnable && mode_lib->ms.cache_display_cfg.plane.HostVMEnable)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8814

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8815

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8821

mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8826

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8842

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[j] == k

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8864

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8876

CalculateUrgentBurstFactor(mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8884

mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8885

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8886

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8887

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8899

locals->cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8900

((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8954

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8968

myPipe->ScalerEnabled = mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8969

myPipe->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8975

myPipe->NumberOfCursors = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9001

CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(locals->SwathWidthY[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9006

CalculatePrefetchSchedule_params->GPUVMPageTableLevels = mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9007

CalculatePrefetchSchedule_params->GPUVMEnable = mode_lib->ms.cache_display_cfg.plane.GPUVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9008

CalculatePrefetchSchedule_params->HostVMEnable = mode_lib->ms.cache_display_cfg.plane.HostVMEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9009

CalculatePrefetchSchedule_params->HostVMMaxNonCachedPageTableLevels = mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9011

CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9013

CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9014

CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9064

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9072

mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9073

mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9086

locals->cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * locals->VRatioPrefetchY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9096

dml_print("DML::%s: k=%0u VRatioY=%f\n", __func__, k, mode_lib->ms.cache_display_cfg.plane.VRatio[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9140

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9170

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9254

mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9255

mode_lib->ms.cache_display_cfg.plane.HostVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9256

mode_lib->ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9257

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9266

mode_lib->ms.cache_display_cfg.plane.VRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9267

mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9285

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9313

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9357

((!mode_lib->ms.support.ImmediateFlipSupport && !mode_lib->ms.cache_display_cfg.plane.HostVMEnable && !s->ImmediateFlipRequirementFinal) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9364

dml_print("DML::%s: HostVMEnable = %u\n", __func__, mode_lib->ms.cache_display_cfg.plane.HostVMEnable);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9414

CalculateWatermarks_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9436

CalculateWatermarks_params->LBBitPerPixel = mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9439

CalculateWatermarks_params->HRatio = mode_lib->ms.cache_display_cfg.plane.HRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9440

CalculateWatermarks_params->HRatioChroma = mode_lib->ms.cache_display_cfg.plane.HRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9441

CalculateWatermarks_params->VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9442

CalculateWatermarks_params->VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9443

CalculateWatermarks_params->VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9444

CalculateWatermarks_params->VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9449

CalculateWatermarks_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9499

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9500

mode_lib->ms.cache_display_cfg.plane.VRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9506

mode_lib->ms.cache_display_cfg.plane.HRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9507

mode_lib->ms.cache_display_cfg.plane.HRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9513

mode_lib->ms.cache_display_cfg.plane.SourceScan,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9514

mode_lib->ms.cache_display_cfg.plane.NumberOfCursors,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9515

mode_lib->ms.cache_display_cfg.plane.CursorWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9516

mode_lib->ms.cache_display_cfg.plane.CursorBPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9537

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9541

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9542

mode_lib->ms.cache_display_cfg.plane.VRatioChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9549

mode_lib->ms.cache_display_cfg.plane.SourceScan,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9590

mode_lib->ms.cache_display_cfg.plane.GPUVMEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9591

mode_lib->ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9632

if (!mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k])

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9657

mode_lib->ms.cache_display_cfg.plane.SourceScan[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9683

if (mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k] && mode_lib->ms.ip.dynamic_metadata_vm_enabled) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9762

if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9769

CalculateStutterEfficiency_params->UseMALLForPStateChange = mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9784

CalculateStutterEfficiency_params->BlendingAndTiming = mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9804

CalculateStutterEfficiency_params->VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9805

CalculateStutterEfficiency_params->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9841

mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9856

mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9876

mode_lib->ms.cache_display_cfg.plane.VRatio,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9877

mode_lib->ms.cache_display_cfg.plane.SourceScan,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

679

struct dml_plane_cfg_st plane;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

404

dml_print("DML: MODE SUPPORT: Host VM or Immediate Flip Supported : %s\n", ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_support_locals.ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j]) ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

543

void dml_print_dml_display_cfg_plane(const struct dml_plane_cfg_st *plane, dml_uint_t num_plane)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

546

dml_print("DML: plane_cfg: GPUVMEnable = %d\n", plane->GPUVMEnable);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

547

dml_print("DML: plane_cfg: HostVMEnable = %d\n", plane->HostVMEnable);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

548

dml_print("DML: plane_cfg: GPUVMMaxPageTableLevels = %d\n", plane->GPUVMMaxPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

549

dml_print("DML: plane_cfg: HostVMMaxPageTableLevels = %d\n", plane->HostVMMaxPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

552

dml_print("DML: plane_cfg: plane=%d, GPUVMMinPageSizeKBytes = %d\n", i, plane->GPUVMMinPageSizeKBytes[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

553

dml_print("DML: plane_cfg: plane=%d, ForceOneRowForFrame = %d\n", i, plane->ForceOneRowForFrame[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

554

dml_print("DML: plane_cfg: plane=%d, PTEBufferModeOverrideEn = %d\n", i, plane->PTEBufferModeOverrideEn[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

555

dml_print("DML: plane_cfg: plane=%d, PTEBufferMode = %d\n", i, plane->PTEBufferMode[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

556

dml_print("DML: plane_cfg: plane=%d, DETSizeOverride = %d\n", i, plane->DETSizeOverride[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

557

dml_print("DML: plane_cfg: plane=%d, UseMALLForStaticScreen = %d\n", i, plane->UseMALLForStaticScreen[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

558

dml_print("DML: plane_cfg: plane=%d, UseMALLForPStateChange = %d\n", i, plane->UseMALLForPStateChange[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

559

dml_print("DML: plane_cfg: plane=%d, BlendingAndTiming = %d\n", i, plane->BlendingAndTiming[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

560

dml_print("DML: plane_cfg: plane=%d, ViewportWidth = %d\n", i, plane->ViewportWidth[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

561

dml_print("DML: plane_cfg: plane=%d, ViewportHeight = %d\n", i, plane->ViewportHeight[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

562

dml_print("DML: plane_cfg: plane=%d, ViewportWidthChroma = %d\n", i, plane->ViewportWidthChroma[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

563

dml_print("DML: plane_cfg: plane=%d, ViewportHeightChroma = %d\n", i, plane->ViewportHeightChroma[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

564

dml_print("DML: plane_cfg: plane=%d, ViewportXStart = %d\n", i, plane->ViewportXStart[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

565

dml_print("DML: plane_cfg: plane=%d, ViewportXStartC = %d\n", i, plane->ViewportXStartC[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

566

dml_print("DML: plane_cfg: plane=%d, ViewportYStart = %d\n", i, plane->ViewportYStart[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

567

dml_print("DML: plane_cfg: plane=%d, ViewportYStartC = %d\n", i, plane->ViewportYStartC[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

568

dml_print("DML: plane_cfg: plane=%d, ViewportStationary = %d\n", i, plane->ViewportStationary[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

569

dml_print("DML: plane_cfg: plane=%d, ScalerEnabled = %d\n", i, plane->ScalerEnabled[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

570

dml_print("DML: plane_cfg: plane=%d, HRatio = %3.2f\n", i, plane->HRatio[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

571

dml_print("DML: plane_cfg: plane=%d, VRatio = %3.2f\n", i, plane->VRatio[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

572

dml_print("DML: plane_cfg: plane=%d, HRatioChroma = %3.2f\n", i, plane->HRatioChroma[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

573

dml_print("DML: plane_cfg: plane=%d, VRatioChroma = %3.2f\n", i, plane->VRatioChroma[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

574

dml_print("DML: plane_cfg: plane=%d, HTaps = %d\n", i, plane->HTaps[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

575

dml_print("DML: plane_cfg: plane=%d, VTaps = %d\n", i, plane->VTaps[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

576

dml_print("DML: plane_cfg: plane=%d, HTapsChroma = %d\n", i, plane->HTapsChroma[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

577

dml_print("DML: plane_cfg: plane=%d, VTapsChroma = %d\n", i, plane->VTapsChroma[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

578

dml_print("DML: plane_cfg: plane=%d, LBBitPerPixel = %d\n", i, plane->LBBitPerPixel[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

579

dml_print("DML: plane_cfg: plane=%d, SourceScan = %d\n", i, plane->SourceScan[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

580

dml_print("DML: plane_cfg: plane=%d, ScalerRecoutWidth = %d\n", i, plane->ScalerRecoutWidth[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

581

dml_print("DML: plane_cfg: plane=%d, NumberOfCursors = %d\n", i, plane->NumberOfCursors[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

582

dml_print("DML: plane_cfg: plane=%d, CursorWidth = %d\n", i, plane->CursorWidth[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

583

dml_print("DML: plane_cfg: plane=%d, CursorBPP = %d\n", i, plane->CursorBPP[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

585

dml_print("DML: plane_cfg: plane=%d, DynamicMetadataEnable = %d\n", i, plane->DynamicMetadataEnable[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

586

dml_print("DML: plane_cfg: plane=%d, DynamicMetadataLinesBeforeActiveRequired = %d\n", i, plane->DynamicMetadataLinesBeforeActiveRequired[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

587

dml_print("DML: plane_cfg: plane=%d, DynamicMetadataTransmittedBytes = %d\n", i, plane->DynamicMetadataTransmittedBytes[i]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

733

if (display_cfg->plane.ViewportWidth[k] > 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

62

__DML_DLL_EXPORT__ void dml_print_dml_display_cfg_plane(const struct dml_plane_cfg_st *plane, dml_uint_t num_plane);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

384

static void populate_dml21_dummy_plane_cfg(struct dml2_plane_parameters *plane, const struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

398

plane->cursor.cursor_bpp = 32;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

400

plane->cursor.cursor_width = 256;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

401

plane->cursor.num_cursors = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

403

plane->composition.viewport.plane0.width = width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

404

plane->composition.viewport.plane0.height = height;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

405

plane->composition.viewport.plane1.width = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

406

plane->composition.viewport.plane1.height = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

408

plane->composition.viewport.stationary = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

409

plane->composition.viewport.plane0.x_start = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

410

plane->composition.viewport.plane0.y_start = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

411

plane->composition.viewport.plane1.x_start = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

412

plane->composition.viewport.plane1.y_start = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

414

plane->composition.scaler_info.enabled = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

415

plane->composition.rotation_angle = dml2_rotation_0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

416

plane->composition.scaler_info.plane0.h_ratio = 1.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

417

plane->composition.scaler_info.plane0.v_ratio = 1.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

418

plane->composition.scaler_info.plane1.h_ratio = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

419

plane->composition.scaler_info.plane1.v_ratio = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

420

plane->composition.scaler_info.plane0.h_taps = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

421

plane->composition.scaler_info.plane0.v_taps = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

422

plane->composition.scaler_info.plane1.h_taps = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

423

plane->composition.scaler_info.plane1.v_taps = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

424

plane->composition.scaler_info.rect_out_width = width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

425

plane->pixel_format = dml2_444_32;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

427

plane->dynamic_meta_data.enable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

428

plane->overrides.gpuvm_min_page_size_kbytes = 256;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

497

struct dml2_plane_parameters *plane, const struct dc_plane_state *plane_state,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

503

plane->cursor.cursor_bpp = 32;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

504

plane->cursor.cursor_width = 256;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

505

plane->cursor.num_cursors = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

510

plane->pixel_format = dml2_420_8;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

514

plane->pixel_format = dml2_420_10;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

520

plane->pixel_format = dml2_444_64;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

524

plane->pixel_format = dml2_444_16;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

527

plane->pixel_format = dml2_444_8;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

530

plane->pixel_format = dml2_rgbe_alpha;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

533

plane->pixel_format = dml2_444_32;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

537

plane->composition.viewport.plane0.height = scaler_data->viewport.height;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

538

plane->composition.viewport.plane0.width = scaler_data->viewport.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

539

plane->composition.viewport.plane1.height = scaler_data->viewport_c.height;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

540

plane->composition.viewport.plane1.width = scaler_data->viewport_c.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

541

plane->composition.viewport.plane0.x_start = scaler_data->viewport.x;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

542

plane->composition.viewport.plane0.y_start = scaler_data->viewport.y;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

543

plane->composition.viewport.plane1.x_start = scaler_data->viewport_c.x;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

544

plane->composition.viewport.plane1.y_start = scaler_data->viewport_c.y;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

545

plane->composition.viewport.stationary = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

546

plane->composition.scaler_info.enabled = scaler_data->ratios.horz.value != dc_fixpt_one.value ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

555

plane->composition.scaler_info.enabled = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

557

(plane->composition.scaler_info.enabled == false)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

563

plane->composition.scaler_info.enabled = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

569

plane->composition.scaler_info.enabled = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

572

if (plane->composition.scaler_info.enabled == false) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

573

plane->composition.scaler_info.plane0.h_ratio = 1.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

574

plane->composition.scaler_info.plane0.v_ratio = 1.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

575

plane->composition.scaler_info.plane1.h_ratio = 1.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

576

plane->composition.scaler_info.plane1.v_ratio = 1.0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

578

plane->composition.scaler_info.plane0.h_ratio = (double)scaler_data->ratios.horz.value / (1ULL << 32);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

579

plane->composition.scaler_info.plane0.v_ratio = (double)scaler_data->ratios.vert.value / (1ULL << 32);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

580

plane->composition.scaler_info.plane1.h_ratio = (double)scaler_data->ratios.horz_c.value / (1ULL << 32);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

581

plane->composition.scaler_info.plane1.v_ratio = (double)scaler_data->ratios.vert_c.value / (1ULL << 32);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

585

plane->composition.scaler_info.plane0.h_taps = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

586

plane->composition.scaler_info.plane1.h_taps = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

588

plane->composition.scaler_info.plane0.h_taps = scaler_data->taps.h_taps;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

589

plane->composition.scaler_info.plane1.h_taps = scaler_data->taps.h_taps_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

592

plane->composition.scaler_info.plane0.v_taps = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

593

plane->composition.scaler_info.plane1.v_taps = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

595

plane->composition.scaler_info.plane0.v_taps = scaler_data->taps.v_taps;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

596

plane->composition.scaler_info.plane1.v_taps = scaler_data->taps.v_taps_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

599

plane->composition.viewport.stationary = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

602

plane->tdlut.setup_for_tdlut = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

607

plane->tdlut.tdlut_addressing_mode = dml2_tdlut_sw_linear;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

610

plane->tdlut.tdlut_addressing_mode = dml2_tdlut_simple_linear;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

616

plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

624

plane->tdlut.setup_for_tdlut |= dml_ctx->config.force_tdlut_enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

626

plane->dynamic_meta_data.enable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

627

plane->dynamic_meta_data.lines_before_active_required = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

628

plane->dynamic_meta_data.transmitted_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

630

plane->composition.scaler_info.rect_out_width = plane_state->dst_rect.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

631

plane->composition.rotation_angle = (enum dml2_rotation_angle) plane_state->rotation;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

632

plane->stream_index = stream_index;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

634

plane->overrides.gpuvm_min_page_size_kbytes = 256;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

636

plane->immediate_flip = plane_state->flip_immediate;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

638

plane->composition.rect_out_height_spans_vactive =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

644

static bool dml21_wrapper_get_plane_id(const struct dc_state *context, unsigned int stream_id, const struct dc_plane_state *plane, unsigned int *plane_id)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

654

if (context->stream_status[i].plane_states[j] == plane) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

681

const struct dc_plane_state *plane, const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

687

if (!dml21_wrapper_get_plane_id(context, stream_id, plane, &plane_id)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

27

unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

36

bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

45

if (state->stream_status[i].plane_states[j] == plane) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

20

bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1938

struct dml2_plane_parameters *plane;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1948

plane = &display_config->display_config.plane_descriptors[plane_index];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1951

plane->overrides.legacy_svp_config = dml2_svp_mode_override_auto;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1954

plane->overrides.reserved_vblank_time_ns = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1957

plane->overrides.uclk_pstate_change_strategy = dml2_uclk_pstate_change_strategy_auto;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1968

struct dml2_plane_parameters *plane;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1972

plane = &display_config->display_config.plane_descriptors[plane_index];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1974

plane->overrides.uclk_pstate_change_strategy = dml2_uclk_pstate_change_strategy_force_drr;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2033

struct dml2_plane_parameters *plane;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2037

plane = &display_config->display_config.plane_descriptors[plane_index];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2039

plane->overrides.reserved_vblank_time_ns = (long)math_max2(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000.0,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2040

plane->overrides.reserved_vblank_time_ns);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2053

struct dml2_plane_parameters *plane;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2057

plane = &display_config->display_config.plane_descriptors[plane_index];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2058

plane->overrides.reserved_vblank_time_ns = (long)(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

524

const struct dml2_plane_parameters *plane;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

535

plane = &params->display_cfg->plane_descriptors[plane_index];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

536

stream = &params->display_cfg->stream_descriptors[plane->stream_index];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

538

num_dpps = odm_combine_factor = params->cfg_support_info->stream_support_info[plane->stream_index].odms_used;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

546

max_per_pipe_vp_p0 = plane->surface.plane0.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

547

temp = (unsigned int)math_ceil(plane->composition.scaler_info.plane0.h_ratio * stream->timing.h_active / odm_combine_factor);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

552

max_per_pipe_vp_p1 = plane->surface.plane1.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

553

temp = (unsigned int)math_ceil(plane->composition.scaler_info.plane1.h_ratio * stream->timing.h_active / odm_combine_factor);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

558

max_per_pipe_vp_p0 = plane->surface.plane0.width / mpc_combine_factor;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

559

max_per_pipe_vp_p1 = plane->surface.plane1.width / mpc_combine_factor;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

584

scaling_transform = plane->composition.scaling_transform;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

591

if (plane->composition.viewport.stationary) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

592

calculate_h_split_for_scaling_transform(plane->surface.plane0.width,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

602

if (plane->composition.viewport.stationary) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

603

calculate_h_split_for_scaling_transform(plane->surface.plane1.width,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

559

const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

58

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

639

const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

654

if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

70

if (state->stream_status[i].plane_states[j] == plane &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

701

const struct dc_plane_state *plane, const struct dc_plane_pipe_pool *pool, unsigned int stream_id, int plane_index)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

707

if (state->res_ctx.pipe_ctx[i].plane_state == plane &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

754

static void map_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state, const struct dc_stream_state *stream, const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

762

if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

767

master_pipe = assign_pipes_to_plane(ctx, state, stream, plane, scratch->odm_info.odm_factor,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

774

plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

788

free_unused_pipes_for_plane(ctx, state, plane, &scratch->pipe_pool, stream->stream_id, plane_index);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

909

const struct dc_plane_state *plane)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

912

int dpp_pipe_count = ctx->config.callbacks.get_dpp_pipes_for_plane(plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1146

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1158

if (context->stream_status[i].plane_states[j] == plane &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1170

static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2, const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1177

if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1305

dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1306

dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1307

dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1308

dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1357

populate_dummy_dml_plane_cfg(&dml_dispcfg->plane, disp_cfg_plane_location,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1360

dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1375

&dml_dispcfg->plane, disp_cfg_plane_location,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1380

dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1381

dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1383

dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1384

dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_disable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1387

dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_disable;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1388

dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1391

dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1412

dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1414

dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

216

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

228

if (state->stream_status[i].plane_states[j] == plane &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

473

if (plane_index + 1 < dml_dispcfg->num_surfaces && dml_dispcfg->plane.BlendingAndTiming[plane_index] != dml_dispcfg->plane.BlendingAndTiming[plane_index + 1])

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

494

dml_dispcfg->plane.DETSizeOverride[plane_index] = max_det_size / in_ctx->config.dcn_pipe_count;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

496

dml_dispcfg->plane.DETSizeOverride[plane_index] = ((max_det_size / num_of_streams) / num_of_planes_per_stream[stream_index] / in_ctx->det_helper_scratch.dpps_per_surface[plane_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

501

if (dml_dispcfg->plane.DETSizeOverride[plane_index] % in_ctx->config.det_segment_size != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

502

dml_dispcfg->plane.DETSizeOverride[plane_index] = dml_dispcfg->plane.DETSizeOverride[plane_index] & ~0x3F;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

505

if (plane_index + 1 < dml_dispcfg->num_surfaces && dml_dispcfg->plane.BlendingAndTiming[plane_index] != dml_dispcfg->plane.BlendingAndTiming[plane_index + 1])

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

124

if (p->cur_display_config->plane.BlendingAndTiming[i] > largest_blend_and_timing)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

125

largest_blend_and_timing = p->cur_display_config->plane.BlendingAndTiming[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

242

planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

101

int (*get_dpp_pipes_for_plane)(const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

137

struct dc_plane_state *plane);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

88

const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

205

struct dml_plane_cfg_st *plane = &mode_lib->ms.cache_display_cfg.plane;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

208

dml_uint_t num_cursors = plane->NumberOfCursors[plane_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1060

(plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

916

struct dc_plane_state *plane = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

945

plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

947

if (!stream || !plane)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

950

if (stream && plane) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

952

plane->address.grph.cursor_cache_addr.quad_part;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

968

plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

969

plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

970

plane->address.page_table_base.quad_part == 0 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

972

dc->hwss.does_plane_fit_in_mall(dc, plane->plane_size.surface_pitch,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

973

plane->plane_size.surface_size.height, plane->format,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

259

struct dc_plane_state *plane = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

300

plane = dc->current_state->stream_status[i].plane_states[j];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

302

if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

303

plane->address.tmz_surface) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1282

struct dc_plane_state *plane = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1319

plane = dc->current_state->stream_status[i].plane_states[j];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1321

if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1322

plane->address.tmz_surface) {

sys/dev/pci/drm/amd/display/dc/inc/resource.h

370

const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

407

int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1061

struct dc_plane_state *plane =

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1065

if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1067

if ((plane->src_rect.width > 1920 ||

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1068

plane->src_rect.height > 1080))

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1173

struct dc_plane_state *plane =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1177

if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1179

if (plane->src_rect.width > plane->dst_rect.width ||

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1180

plane->src_rect.height > plane->dst_rect.height)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1183

if (plane->src_rect.width >= 3840)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1187

if (plane->src_rect.width >= 3840)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1189

if (!plane->dcc.enable)

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1130

const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1147

plane->time.prev_update_time_in_us;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

127

const struct dc_plane_state *plane,

sys/dev/pci/drm/apple/apple_drv.c

111

static void apple_plane_atomic_update(struct drm_plane *plane,

sys/dev/pci/drm/apple/apple_drv.c

122

static void apple_plane_cleanup(struct drm_plane *plane)

sys/dev/pci/drm/apple/apple_drv.c

124

drm_plane_cleanup(plane);

sys/dev/pci/drm/apple/apple_drv.c

125

kfree(plane);

sys/dev/pci/drm/apple/apple_drv.c

166

struct drm_plane *plane;

sys/dev/pci/drm/apple/apple_drv.c

168

plane = kzalloc(sizeof(*plane), GFP_KERNEL);

sys/dev/pci/drm/apple/apple_drv.c

170

ret = drm_universal_plane_init(dev, plane, possible_crtcs,

sys/dev/pci/drm/apple/apple_drv.c

177

drm_plane_helper_add(plane, &apple_plane_helper_funcs);

sys/dev/pci/drm/apple/apple_drv.c

179

return plane;

sys/dev/pci/drm/apple/apple_drv.c

77

static int apple_plane_atomic_check(struct drm_plane *plane,

sys/dev/pci/drm/apple/apple_drv.c

83

new_plane_state = drm_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/apple/dcp.c

218

struct drm_plane *plane;

sys/dev/pci/drm/apple/dcp.c

234

for_each_new_plane_in_state(state, plane, new_state, plane_idx) {

sys/dev/pci/drm/apple/iomfb_template.c

1258

struct drm_plane *plane;

sys/dev/pci/drm/apple/iomfb_template.c

1290

for_each_oldnew_plane_in_state(state, plane, old_state, new_state, plane_idx) {

sys/dev/pci/drm/clients/drm_log.c

180

static u32 drm_log_find_usable_format(struct drm_plane *plane)

sys/dev/pci/drm/clients/drm_log.c

184

for (i = 0; i < plane->format_count; i++)

sys/dev/pci/drm/clients/drm_log.c

185

if (drm_draw_color_from_xrgb8888(0xffffff, plane->format_types[i]) != 0)

sys/dev/pci/drm/clients/drm_log.c

186

return plane->format_types[i];

sys/dev/pci/drm/drm_atomic.c

1440

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic.c

1448

drm_for_each_plane_mask(plane, state->dev, old_crtc_state->plane_mask) {

sys/dev/pci/drm/drm_atomic.c

1450

drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_atomic.c

1474

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic.c

1493

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic.c

1497

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic.c

1630

int __drm_atomic_helper_disable_plane(struct drm_plane *plane,

sys/dev/pci/drm/drm_atomic.c

1820

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic.c

1837

for_each_new_plane_in_state(state, plane, plane_state, i)

sys/dev/pci/drm/drm_atomic.c

1855

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic.c

1864

list_for_each_entry(plane, &config->plane_list, head) {

sys/dev/pci/drm/drm_atomic.c

1866

drm_modeset_lock(&plane->mutex, NULL);

sys/dev/pci/drm/drm_atomic.c

1867

drm_atomic_plane_print_state(p, plane->state);

sys/dev/pci/drm/drm_atomic.c

1869

drm_modeset_unlock(&plane->mutex);

sys/dev/pci/drm/drm_atomic.c

239

struct drm_plane *plane = state->planes[i].ptr;

sys/dev/pci/drm/drm_atomic.c

241

if (!plane)

sys/dev/pci/drm/drm_atomic.c

244

plane->funcs->atomic_destroy_state(plane,

sys/dev/pci/drm/drm_atomic.c

525

struct drm_plane *plane)

sys/dev/pci/drm/drm_atomic.c

527

int ret, index = drm_plane_index(plane);

sys/dev/pci/drm/drm_atomic.c

533

WARN_ON(plane->fb);

sys/dev/pci/drm/drm_atomic.c

534

WARN_ON(plane->old_fb);

sys/dev/pci/drm/drm_atomic.c

535

WARN_ON(plane->crtc);

sys/dev/pci/drm/drm_atomic.c

537

plane_state = drm_atomic_get_existing_plane_state(state, plane);

sys/dev/pci/drm/drm_atomic.c

541

ret = drm_modeset_lock(&plane->mutex, state->acquire_ctx);

sys/dev/pci/drm/drm_atomic.c

545

plane_state = plane->funcs->atomic_duplicate_state(plane);

sys/dev/pci/drm/drm_atomic.c

550

state->planes[index].ptr = plane;

sys/dev/pci/drm/drm_atomic.c

551

state->planes[index].old_state = plane->state;

sys/dev/pci/drm/drm_atomic.c

555

drm_dbg_atomic(plane->dev, "Added [PLANE:%d:%s] %p state to %p\n",

sys/dev/pci/drm/drm_atomic.c

556

plane->base.id, plane->name, plane_state, state);

sys/dev/pci/drm/drm_atomic.c

602

struct drm_plane *plane = new_plane_state->plane;

sys/dev/pci/drm/drm_atomic.c

611

drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] CRTC set but no FB\n",

sys/dev/pci/drm/drm_atomic.c

612

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic.c

615

drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] FB set but no CRTC\n",

sys/dev/pci/drm/drm_atomic.c

616

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic.c

625

if (!(plane->possible_crtcs & drm_crtc_mask(crtc))) {

sys/dev/pci/drm/drm_atomic.c

626

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic.c

629

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic.c

634

if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) {

sys/dev/pci/drm/drm_atomic.c

635

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic.c

637

plane->base.id, plane->name,

sys/dev/pci/drm/drm_atomic.c

647

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic.c

649

plane->base.id, plane->name,

sys/dev/pci/drm/drm_atomic.c

663

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic.c

666

plane->base.id, plane->name,

sys/dev/pci/drm/drm_atomic.c

690

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic.c

692

plane->base.id, plane->name, clips->x1,

sys/dev/pci/drm/drm_atomic.c

701

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic.c

703

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic.c

713

struct drm_plane *plane = state->plane;

sys/dev/pci/drm/drm_atomic.c

717

drm_printf(p, "plane[%u]: %s\n", plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic.c

732

if (plane->funcs->atomic_print_state)

sys/dev/pci/drm/drm_atomic.c

733

plane->funcs->atomic_print_state(p, state);

sys/dev/pci/drm/drm_atomic_helper.c

1029

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

1033

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

1036

WARN_ON(!drm_modeset_is_locked(&plane->mutex));

sys/dev/pci/drm/drm_atomic_helper.c

1038

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

1040

drm_atomic_helper_plane_changed(state, old_plane_state, new_plane_state, plane);

sys/dev/pci/drm/drm_atomic_helper.c

1047

ret = funcs->atomic_check(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

1049

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_helper.c

1051

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic_helper.c

1786

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

1811

for_each_new_plane_in_state (state, plane, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

1843

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

1849

for_each_new_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

2116

struct drm_plane *plane = NULL;

sys/dev/pci/drm/drm_atomic_helper.c

2127

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)

sys/dev/pci/drm/drm_atomic_helper.c

2141

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic_helper.c

2145

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2149

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic_helper.c

2156

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic_helper.c

2169

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic_helper.c

2173

ret = funcs->atomic_async_check(plane, state, false);

sys/dev/pci/drm/drm_atomic_helper.c

2177

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic_helper.c

2198

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

2203

for_each_new_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

2205

struct drm_framebuffer *old_fb = plane->state->fb;

sys/dev/pci/drm/drm_atomic_helper.c

2207

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2208

funcs->atomic_async_update(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

2215

WARN_ON_ONCE(plane->state->fb != new_fb);

sys/dev/pci/drm/drm_atomic_helper.c

2216

WARN_ON_ONCE(plane->state->crtc_x != plane_state->crtc_x);

sys/dev/pci/drm/drm_atomic_helper.c

2217

WARN_ON_ONCE(plane->state->crtc_y != plane_state->crtc_y);

sys/dev/pci/drm/drm_atomic_helper.c

2218

WARN_ON_ONCE(plane->state->src_x != plane_state->src_x);

sys/dev/pci/drm/drm_atomic_helper.c

2219

WARN_ON_ONCE(plane->state->src_y != plane_state->src_y);

sys/dev/pci/drm/drm_atomic_helper.c

2521

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

2599

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

2606

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_helper.c

2608

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic_helper.c

2644

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

2667

for_each_old_plane_in_state(state, plane, old_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

2670

drm_err(plane->dev,

sys/dev/pci/drm/drm_atomic_helper.c

2672

plane->base.id, plane->name);

sys/dev/pci/drm/drm_atomic_helper.c

2823

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

2836

for_each_new_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

2839

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2842

ret = funcs->prepare_fb(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2851

ret = drm_gem_plane_helper_prepare_fb(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2857

for_each_new_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

2858

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2861

ret = funcs->begin_fb_access(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2870

for_each_new_plane_in_state(state, plane, new_plane_state, j) {

sys/dev/pci/drm/drm_atomic_helper.c

2871

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2877

funcs->end_fb_access(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2881

for_each_new_plane_in_state(state, plane, new_plane_state, j) {

sys/dev/pci/drm/drm_atomic_helper.c

2887

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2890

funcs->cleanup_fb(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2910

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

2914

for_each_new_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

2915

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2918

funcs->end_fb_access(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2921

for_each_new_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

2922

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

2925

funcs->cleanup_fb(plane, new_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

2982

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

3002

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

3006

funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3040

funcs->atomic_disable(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

3042

funcs->atomic_update(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

3046

funcs->atomic_enable(plane, state);

sys/dev/pci/drm/drm_atomic_helper.c

3069

for_each_old_plane_in_state(state, plane, old_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

3070

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3073

funcs->end_fb_access(plane, old_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

3103

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

3113

drm_for_each_plane_mask(plane, crtc->dev, plane_mask) {

sys/dev/pci/drm/drm_atomic_helper.c

3115

drm_atomic_get_old_plane_state(old_state, plane);

sys/dev/pci/drm/drm_atomic_helper.c

3117

drm_atomic_get_new_plane_state(old_state, plane);

sys/dev/pci/drm/drm_atomic_helper.c

3121

plane_funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3132

plane_funcs->atomic_disable(plane, old_state);

sys/dev/pci/drm/drm_atomic_helper.c

3134

plane_funcs->atomic_update(plane, old_state);

sys/dev/pci/drm/drm_atomic_helper.c

3138

plane_funcs->atomic_enable(plane, old_state);

sys/dev/pci/drm/drm_atomic_helper.c

3171

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

3176

drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {

sys/dev/pci/drm/drm_atomic_helper.c

3178

plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3185

plane_funcs->atomic_disable(plane, NULL);

sys/dev/pci/drm/drm_atomic_helper.c

3209

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

3213

for_each_old_plane_in_state(state, plane, old_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

3214

const struct drm_plane_helper_funcs *funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_helper.c

3217

funcs->cleanup_fb(plane, old_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

3265

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

3303

for_each_old_plane_in_state(state, plane, old_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

3345

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

3346

WARN_ON(plane->state != old_plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

3352

plane->state = new_plane_state;

sys/dev/pci/drm/drm_atomic_helper.c

3390

int drm_atomic_helper_update_plane(struct drm_plane *plane,

sys/dev/pci/drm/drm_atomic_helper.c

3403

state = drm_atomic_state_alloc(plane->dev);

sys/dev/pci/drm/drm_atomic_helper.c

3408

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_atomic_helper.c

3427

if (plane == crtc->cursor)

sys/dev/pci/drm/drm_atomic_helper.c

3447

int drm_atomic_helper_disable_plane(struct drm_plane *plane,

sys/dev/pci/drm/drm_atomic_helper.c

3454

state = drm_atomic_state_alloc(plane->dev);

sys/dev/pci/drm/drm_atomic_helper.c

3459

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_atomic_helper.c

3465

if (plane_state->crtc && plane_state->crtc->cursor == plane)

sys/dev/pci/drm/drm_atomic_helper.c

3468

ret = __drm_atomic_helper_disable_plane(plane, plane_state);

sys/dev/pci/drm/drm_atomic_helper.c

3553

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

3592

for_each_new_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/drm_atomic_helper.c

3717

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

3738

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_atomic_helper.c

3741

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_atomic_helper.c

3849

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

3858

for_each_new_plane_in_state(state, plane, new_plane_state, i)

sys/dev/pci/drm/drm_atomic_helper.c

3859

state->planes[i].old_state = plane->state;

sys/dev/pci/drm/drm_atomic_helper.c

3916

struct drm_plane *plane = crtc->primary;

sys/dev/pci/drm/drm_atomic_helper.c

3928

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_atomic_helper.c

3972

struct drm_plane *plane = crtc->primary;

sys/dev/pci/drm/drm_atomic_helper.c

3976

state = drm_atomic_state_alloc(plane->dev);

sys/dev/pci/drm/drm_atomic_helper.c

4016

struct drm_plane *plane = crtc->primary;

sys/dev/pci/drm/drm_atomic_helper.c

4021

state = drm_atomic_state_alloc(plane->dev);

sys/dev/pci/drm/drm_atomic_helper.c

82

struct drm_plane *plane)

sys/dev/pci/drm/drm_atomic_helper.c

929

drm_dbg_kms(plane_state->plane->dev,

sys/dev/pci/drm/drm_atomic_helper.c

940

drm_dbg_kms(plane_state->plane->dev,

sys/dev/pci/drm/drm_atomic_helper.c

965

drm_dbg_kms(plane_state->plane->dev,

sys/dev/pci/drm/drm_atomic_helper.c

993

struct drm_plane *plane;

sys/dev/pci/drm/drm_atomic_helper.c

996

drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {

sys/dev/pci/drm/drm_atomic_helper.c

997

if (plane->type == DRM_PLANE_TYPE_PRIMARY)

sys/dev/pci/drm/drm_atomic_state_helper.c

247

struct drm_plane *plane)

sys/dev/pci/drm/drm_atomic_state_helper.c

251

plane_state->plane = plane;

sys/dev/pci/drm/drm_atomic_state_helper.c

257

if (plane->color_encoding_property) {

sys/dev/pci/drm/drm_atomic_state_helper.c

258

if (!drm_object_property_get_default_value(&plane->base,

sys/dev/pci/drm/drm_atomic_state_helper.c

259

plane->color_encoding_property,

sys/dev/pci/drm/drm_atomic_state_helper.c

264

if (plane->color_range_property) {

sys/dev/pci/drm/drm_atomic_state_helper.c

265

if (!drm_object_property_get_default_value(&plane->base,

sys/dev/pci/drm/drm_atomic_state_helper.c

266

plane->color_range_property,

sys/dev/pci/drm/drm_atomic_state_helper.c

271

if (plane->zpos_property) {

sys/dev/pci/drm/drm_atomic_state_helper.c

272

if (!drm_object_property_get_default_value(&plane->base,

sys/dev/pci/drm/drm_atomic_state_helper.c

273

plane->zpos_property,

sys/dev/pci/drm/drm_atomic_state_helper.c

280

if (plane->hotspot_x_property) {

sys/dev/pci/drm/drm_atomic_state_helper.c

281

if (!drm_object_property_get_default_value(&plane->base,

sys/dev/pci/drm/drm_atomic_state_helper.c

282

plane->hotspot_x_property,

sys/dev/pci/drm/drm_atomic_state_helper.c

287

if (plane->hotspot_y_property) {

sys/dev/pci/drm/drm_atomic_state_helper.c

288

if (!drm_object_property_get_default_value(&plane->base,

sys/dev/pci/drm/drm_atomic_state_helper.c

289

plane->hotspot_y_property,

sys/dev/pci/drm/drm_atomic_state_helper.c

308

void __drm_atomic_helper_plane_reset(struct drm_plane *plane,

sys/dev/pci/drm/drm_atomic_state_helper.c

312

__drm_atomic_helper_plane_state_reset(plane_state, plane);

sys/dev/pci/drm/drm_atomic_state_helper.c

314

plane->state = plane_state;

sys/dev/pci/drm/drm_atomic_state_helper.c

325

void drm_atomic_helper_plane_reset(struct drm_plane *plane)

sys/dev/pci/drm/drm_atomic_state_helper.c

327

if (plane->state)

sys/dev/pci/drm/drm_atomic_state_helper.c

328

__drm_atomic_helper_plane_destroy_state(plane->state);

sys/dev/pci/drm/drm_atomic_state_helper.c

330

kfree(plane->state);

sys/dev/pci/drm/drm_atomic_state_helper.c

331

plane->state = kzalloc(sizeof(*plane->state), GFP_KERNEL);

sys/dev/pci/drm/drm_atomic_state_helper.c

332

if (plane->state)

sys/dev/pci/drm/drm_atomic_state_helper.c

333

__drm_atomic_helper_plane_reset(plane, plane->state);

sys/dev/pci/drm/drm_atomic_state_helper.c

345

void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane,

sys/dev/pci/drm/drm_atomic_state_helper.c

348

memcpy(state, plane->state, sizeof(*state));

sys/dev/pci/drm/drm_atomic_state_helper.c

368

drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane)

sys/dev/pci/drm/drm_atomic_state_helper.c

372

if (WARN_ON(!plane->state))

sys/dev/pci/drm/drm_atomic_state_helper.c

377

__drm_atomic_helper_plane_duplicate_state(plane, state);

sys/dev/pci/drm/drm_atomic_state_helper.c

414

void drm_atomic_helper_plane_destroy_state(struct drm_plane *plane,

sys/dev/pci/drm/drm_atomic_uapi.c

1070

struct drm_plane *plane = obj_to_plane(obj);

sys/dev/pci/drm/drm_atomic_uapi.c

1072

struct drm_mode_config *config = &plane->dev->mode_config;

sys/dev/pci/drm/drm_atomic_uapi.c

1073

const struct drm_plane_helper_funcs *plane_funcs = plane->helper_private;

sys/dev/pci/drm/drm_atomic_uapi.c

1075

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_atomic_uapi.c

1083

ret = drm_atomic_plane_get_property(plane, plane_state,

sys/dev/pci/drm/drm_atomic_uapi.c

1094

if (ret && plane->type != DRM_PLANE_TYPE_PRIMARY) {

sys/dev/pci/drm/drm_atomic_uapi.c

1097

ret = plane_funcs->atomic_async_check(plane, state, true);

sys/dev/pci/drm/drm_atomic_uapi.c

1102

obj->id, plane->name);

sys/dev/pci/drm/drm_atomic_uapi.c

1108

ret = drm_atomic_plane_set_property(plane,

sys/dev/pci/drm/drm_atomic_uapi.c

193

struct drm_plane *plane = plane_state->plane;

sys/dev/pci/drm/drm_atomic_uapi.c

204

crtc_state->plane_mask &= ~drm_plane_mask(plane);

sys/dev/pci/drm/drm_atomic_uapi.c

214

crtc_state->plane_mask |= drm_plane_mask(plane);

sys/dev/pci/drm/drm_atomic_uapi.c

218

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_uapi.c

220

plane->base.id, plane->name, plane_state,

sys/dev/pci/drm/drm_atomic_uapi.c

223

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_uapi.c

225

plane->base.id, plane->name, plane_state);

sys/dev/pci/drm/drm_atomic_uapi.c

245

struct drm_plane *plane = plane_state->plane;

sys/dev/pci/drm/drm_atomic_uapi.c

248

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_uapi.c

250

fb->base.id, plane->base.id, plane->name,

sys/dev/pci/drm/drm_atomic_uapi.c

253

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_uapi.c

255

plane->base.id, plane->name, plane_state);

sys/dev/pci/drm/drm_atomic_uapi.c

473

static int drm_atomic_plane_set_property(struct drm_plane *plane,

sys/dev/pci/drm/drm_atomic_uapi.c

477

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_atomic_uapi.c

526

} else if (property == plane->alpha_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

528

} else if (property == plane->blend_mode_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

530

} else if (property == plane->rotation_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

532

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_uapi.c

534

plane->base.id, plane->name, val);

sys/dev/pci/drm/drm_atomic_uapi.c

538

} else if (property == plane->zpos_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

540

} else if (property == plane->color_encoding_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

542

} else if (property == plane->color_range_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

552

} else if (property == plane->scaling_filter_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

554

} else if (plane->funcs->atomic_set_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

555

return plane->funcs->atomic_set_property(plane, state,

sys/dev/pci/drm/drm_atomic_uapi.c

557

} else if (property == plane->hotspot_x_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

558

if (plane->type != DRM_PLANE_TYPE_CURSOR) {

sys/dev/pci/drm/drm_atomic_uapi.c

559

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_uapi.c

561

plane->base.id, plane->name, val);

sys/dev/pci/drm/drm_atomic_uapi.c

565

} else if (property == plane->hotspot_y_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

566

if (plane->type != DRM_PLANE_TYPE_CURSOR) {

sys/dev/pci/drm/drm_atomic_uapi.c

567

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_uapi.c

569

plane->base.id, plane->name, val);

sys/dev/pci/drm/drm_atomic_uapi.c

574

drm_dbg_atomic(plane->dev,

sys/dev/pci/drm/drm_atomic_uapi.c

576

plane->base.id, plane->name,

sys/dev/pci/drm/drm_atomic_uapi.c

585

drm_atomic_plane_get_property(struct drm_plane *plane,

sys/dev/pci/drm/drm_atomic_uapi.c

589

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_atomic_uapi.c

614

} else if (property == plane->alpha_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

616

} else if (property == plane->blend_mode_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

618

} else if (property == plane->rotation_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

620

} else if (property == plane->zpos_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

622

} else if (property == plane->color_encoding_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

624

} else if (property == plane->color_range_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

629

} else if (property == plane->scaling_filter_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

631

} else if (plane->funcs->atomic_get_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

632

return plane->funcs->atomic_get_property(plane, state, property, val);

sys/dev/pci/drm/drm_atomic_uapi.c

633

} else if (property == plane->hotspot_x_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

635

} else if (property == plane->hotspot_y_property) {

sys/dev/pci/drm/drm_atomic_uapi.c

640

plane->base.id, plane->name,

sys/dev/pci/drm/drm_atomic_uapi.c

907

struct drm_plane *plane = obj_to_plane(obj);

sys/dev/pci/drm/drm_atomic_uapi.c

909

WARN_ON(!drm_modeset_is_locked(&plane->mutex));

sys/dev/pci/drm/drm_atomic_uapi.c

910

ret = drm_atomic_plane_get_property(plane,

sys/dev/pci/drm/drm_atomic_uapi.c

911

plane->state, property, val);

sys/dev/pci/drm/drm_blend.c

225

int drm_plane_create_alpha_property(struct drm_plane *plane)

sys/dev/pci/drm/drm_blend.c

229

prop = drm_property_create_range(plane->dev, 0, "alpha",

sys/dev/pci/drm/drm_blend.c

234

drm_object_attach_property(&plane->base, prop, DRM_BLEND_ALPHA_OPAQUE);

sys/dev/pci/drm/drm_blend.c

235

plane->alpha_property = prop;

sys/dev/pci/drm/drm_blend.c

237

if (plane->state)

sys/dev/pci/drm/drm_blend.c

238

plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE;

sys/dev/pci/drm/drm_blend.c

278

int drm_plane_create_rotation_property(struct drm_plane *plane,

sys/dev/pci/drm/drm_blend.c

296

prop = drm_property_create_bitmask(plane->dev, 0, "rotation",

sys/dev/pci/drm/drm_blend.c

302

drm_object_attach_property(&plane->base, prop, rotation);

sys/dev/pci/drm/drm_blend.c

304

if (plane->state)

sys/dev/pci/drm/drm_blend.c

305

plane->state->rotation = rotation;

sys/dev/pci/drm/drm_blend.c

307

plane->rotation_property = prop;

sys/dev/pci/drm/drm_blend.c

375

int drm_plane_create_zpos_property(struct drm_plane *plane,

sys/dev/pci/drm/drm_blend.c

381

prop = drm_property_create_range(plane->dev, 0, "zpos", min, max);

sys/dev/pci/drm/drm_blend.c

385

drm_object_attach_property(&plane->base, prop, zpos);

sys/dev/pci/drm/drm_blend.c

387

plane->zpos_property = prop;

sys/dev/pci/drm/drm_blend.c

389

if (plane->state) {

sys/dev/pci/drm/drm_blend.c

390

plane->state->zpos = zpos;

sys/dev/pci/drm/drm_blend.c

391

plane->state->normalized_zpos = zpos;

sys/dev/pci/drm/drm_blend.c

414

int drm_plane_create_zpos_immutable_property(struct drm_plane *plane,

sys/dev/pci/drm/drm_blend.c

419

prop = drm_property_create_range(plane->dev, DRM_MODE_PROP_IMMUTABLE,

sys/dev/pci/drm/drm_blend.c

424

drm_object_attach_property(&plane->base, prop, zpos);

sys/dev/pci/drm/drm_blend.c

426

plane->zpos_property = prop;

sys/dev/pci/drm/drm_blend.c

428

if (plane->state) {

sys/dev/pci/drm/drm_blend.c

429

plane->state->zpos = zpos;

sys/dev/pci/drm/drm_blend.c

430

plane->state->normalized_zpos = zpos;

sys/dev/pci/drm/drm_blend.c

445

return sa->plane->base.id - sb->plane->base.id;

sys/dev/pci/drm/drm_blend.c

455

struct drm_plane *plane;

sys/dev/pci/drm/drm_blend.c

470

drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {

sys/dev/pci/drm/drm_blend.c

472

drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_blend.c

479

plane->base.id, plane->name, plane_state->zpos);

sys/dev/pci/drm/drm_blend.c

485

plane = states[i]->plane;

sys/dev/pci/drm/drm_blend.c

489

plane->base.id, plane->name, i);

sys/dev/pci/drm/drm_blend.c

521

struct drm_plane *plane;

sys/dev/pci/drm/drm_blend.c

525

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {

sys/dev/pci/drm/drm_blend.c

577

int drm_plane_create_blend_mode_property(struct drm_plane *plane,

sys/dev/pci/drm/drm_blend.c

580

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_blend.c

618

drm_object_attach_property(&plane->base, prop, DRM_MODE_BLEND_PREMULTI);

sys/dev/pci/drm/drm_blend.c

619

plane->blend_mode_property = prop;

sys/dev/pci/drm/drm_client_modeset.c

1031

!plane->rotation_property)

sys/dev/pci/drm/drm_client_modeset.c

1034

for (i = 0; i < plane->rotation_property->num_values; i++)

sys/dev/pci/drm/drm_client_modeset.c

1035

valid_mask |= (1ULL << plane->rotation_property->values[i]);

sys/dev/pci/drm/drm_client_modeset.c

1047

struct drm_plane *plane;

sys/dev/pci/drm/drm_client_modeset.c

1063

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_client_modeset.c

1066

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_client_modeset.c

1075

if (plane->type == DRM_PLANE_TYPE_PRIMARY)

sys/dev/pci/drm/drm_client_modeset.c

1078

ret = __drm_atomic_helper_disable_plane(plane, plane_state);

sys/dev/pci/drm/drm_client_modeset.c

1138

struct drm_plane *plane;

sys/dev/pci/drm/drm_client_modeset.c

1142

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_client_modeset.c

1143

if (plane->type != DRM_PLANE_TYPE_PRIMARY)

sys/dev/pci/drm/drm_client_modeset.c

1144

drm_plane_force_disable(plane);

sys/dev/pci/drm/drm_client_modeset.c

1146

if (plane->rotation_property)

sys/dev/pci/drm/drm_client_modeset.c

1147

drm_mode_plane_set_obj_prop(plane,

sys/dev/pci/drm/drm_client_modeset.c

1148

plane->rotation_property,

sys/dev/pci/drm/drm_client_modeset.c

973

struct drm_plane *plane = modeset->crtc->primary;

sys/dev/pci/drm/drm_color_mgmt.c

531

int drm_plane_create_color_properties(struct drm_plane *plane,

sys/dev/pci/drm/drm_color_mgmt.c

537

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_color_mgmt.c

567

plane->color_encoding_property = prop;

sys/dev/pci/drm/drm_color_mgmt.c

568

drm_object_attach_property(&plane->base, prop, default_encoding);

sys/dev/pci/drm/drm_color_mgmt.c

569

if (plane->state)

sys/dev/pci/drm/drm_color_mgmt.c

570

plane->state->color_encoding = default_encoding;

sys/dev/pci/drm/drm_color_mgmt.c

586

plane->color_range_property = prop;

sys/dev/pci/drm/drm_color_mgmt.c

587

drm_object_attach_property(&plane->base, prop, default_range);

sys/dev/pci/drm/drm_color_mgmt.c

588

if (plane->state)

sys/dev/pci/drm/drm_color_mgmt.c

589

plane->state->color_range = default_range;

sys/dev/pci/drm/drm_crtc.c

531

struct drm_plane *plane;

sys/dev/pci/drm/drm_crtc.c

540

plane = crtc->primary;

sys/dev/pci/drm/drm_crtc.c

544

drm_modeset_lock(&plane->mutex, NULL);

sys/dev/pci/drm/drm_crtc.c

545

if (plane->state && plane->state->fb)

sys/dev/pci/drm/drm_crtc.c

546

crtc_resp->fb_id = plane->state->fb->base.id;

sys/dev/pci/drm/drm_crtc.c

547

else if (!plane->state && plane->fb)

sys/dev/pci/drm/drm_crtc.c

548

crtc_resp->fb_id = plane->fb->base.id;

sys/dev/pci/drm/drm_crtc.c

552

if (plane->state) {

sys/dev/pci/drm/drm_crtc.c

553

crtc_resp->x = plane->state->src_x >> 16;

sys/dev/pci/drm/drm_crtc.c

554

crtc_resp->y = plane->state->src_y >> 16;

sys/dev/pci/drm/drm_crtc.c

556

drm_modeset_unlock(&plane->mutex);

sys/dev/pci/drm/drm_crtc.c

601

struct drm_plane *plane = tmp->primary;

sys/dev/pci/drm/drm_crtc.c

603

plane->old_fb = plane->fb;

sys/dev/pci/drm/drm_crtc.c

610

struct drm_plane *plane = crtc->primary;

sys/dev/pci/drm/drm_crtc.c

612

plane->crtc = fb ? crtc : NULL;

sys/dev/pci/drm/drm_crtc.c

613

plane->fb = fb;

sys/dev/pci/drm/drm_crtc.c

617

struct drm_plane *plane = tmp->primary;

sys/dev/pci/drm/drm_crtc.c

619

if (plane->fb)

sys/dev/pci/drm/drm_crtc.c

620

drm_framebuffer_get(plane->fb);

sys/dev/pci/drm/drm_crtc.c

621

if (plane->old_fb)

sys/dev/pci/drm/drm_crtc.c

622

drm_framebuffer_put(plane->old_fb);

sys/dev/pci/drm/drm_crtc.c

623

plane->old_fb = NULL;

sys/dev/pci/drm/drm_crtc.c

698

struct drm_plane *plane;

sys/dev/pci/drm/drm_crtc.c

724

plane = crtc->primary;

sys/dev/pci/drm/drm_crtc.c

727

if (crtc_req->mode_valid && !drm_lease_held(file_priv, plane->base.id))

sys/dev/pci/drm/drm_crtc.c

739

if (plane->state)

sys/dev/pci/drm/drm_crtc.c

740

old_fb = plane->state->fb;

sys/dev/pci/drm/drm_crtc.c

742

old_fb = plane->fb;

sys/dev/pci/drm/drm_crtc.c

791

if (!plane->format_default) {

sys/dev/pci/drm/drm_crtc.c

792

if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) {

sys/dev/pci/drm/drm_crtc_internal.h

247

int __drm_atomic_helper_disable_plane(struct drm_plane *plane,

sys/dev/pci/drm/drm_damage_helper.c

118

struct drm_plane *plane;

sys/dev/pci/drm/drm_damage_helper.c

161

drm_for_each_plane(plane, fb->dev) {

sys/dev/pci/drm/drm_damage_helper.c

164

ret = drm_modeset_lock(&plane->mutex, state->acquire_ctx);

sys/dev/pci/drm/drm_damage_helper.c

168

if (plane->state->fb != fb) {

sys/dev/pci/drm/drm_damage_helper.c

169

drm_modeset_unlock(&plane->mutex);

sys/dev/pci/drm/drm_damage_helper.c

173

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_fb_dma_helper.c

12

KASSERT(plane == 0);

sys/dev/pci/drm/drm_fb_dma_helper.c

13

obj = fb->obj[plane];

sys/dev/pci/drm/drm_fb_dma_helper.c

8

drm_fb_dma_get_gem_obj(struct drm_framebuffer *fb, unsigned int plane)

sys/dev/pci/drm/drm_fb_helper.c

1539

struct drm_plane *plane = crtc->primary;

sys/dev/pci/drm/drm_fb_helper.c

1551

plane->format_types,

sys/dev/pci/drm/drm_fb_helper.c

1552

plane->format_count,

sys/dev/pci/drm/drm_fb_helper.c

1564

plane->format_types,

sys/dev/pci/drm/drm_fb_helper.c

1565

plane->format_count,

sys/dev/pci/drm/drm_fourcc.c

453

int plane)

sys/dev/pci/drm/drm_fourcc.c

455

if (!info || plane < 0 || plane >= info->num_planes)

sys/dev/pci/drm/drm_fourcc.c

458

if (!info->block_w[plane])

sys/dev/pci/drm/drm_fourcc.c

460

return info->block_w[plane];

sys/dev/pci/drm/drm_fourcc.c

473

int plane)

sys/dev/pci/drm/drm_fourcc.c

475

if (!info || plane < 0 || plane >= info->num_planes)

sys/dev/pci/drm/drm_fourcc.c

478

if (!info->block_h[plane])

sys/dev/pci/drm/drm_fourcc.c

480

return info->block_h[plane];

sys/dev/pci/drm/drm_fourcc.c

492

unsigned int drm_format_info_bpp(const struct drm_format_info *info, int plane)

sys/dev/pci/drm/drm_fourcc.c

494

if (!info || plane < 0 || plane >= info->num_planes)

sys/dev/pci/drm/drm_fourcc.c

497

return info->char_per_block[plane] * 8 /

sys/dev/pci/drm/drm_fourcc.c

498

(drm_format_info_block_width(info, plane) *

sys/dev/pci/drm/drm_fourcc.c

499

drm_format_info_block_height(info, plane));

sys/dev/pci/drm/drm_fourcc.c

514

int plane, unsigned int buffer_width)

sys/dev/pci/drm/drm_fourcc.c

516

if (!info || plane < 0 || plane >= info->num_planes)

sys/dev/pci/drm/drm_fourcc.c

519

return DIV_ROUND_UP_ULL((u64)buffer_width * info->char_per_block[plane],

sys/dev/pci/drm/drm_fourcc.c

520

drm_format_info_block_width(info, plane) *

sys/dev/pci/drm/drm_fourcc.c

521

drm_format_info_block_height(info, plane));

sys/dev/pci/drm/drm_framebuffer.c

1008

struct drm_plane *plane;

sys/dev/pci/drm/drm_framebuffer.c

1031

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_framebuffer.c

1034

if (plane->state->fb != fb)

sys/dev/pci/drm/drm_framebuffer.c

1039

plane->base.id, plane->name, fb->base.id);

sys/dev/pci/drm/drm_framebuffer.c

1041

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/drm_framebuffer.c

1047

if (disable_crtcs && plane_state->crtc->primary == plane) {

sys/dev/pci/drm/drm_framebuffer.c

1072

plane_mask |= drm_plane_mask(plane);

sys/dev/pci/drm/drm_framebuffer.c

1111

struct drm_plane *plane;

sys/dev/pci/drm/drm_framebuffer.c

1127

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_framebuffer.c

1128

if (plane->fb == fb) {

sys/dev/pci/drm/drm_framebuffer.c

1131

plane->base.id, plane->name, fb->base.id);

sys/dev/pci/drm/drm_framebuffer.c

1132

drm_plane_force_disable(plane);

sys/dev/pci/drm/drm_gem_framebuffer_helper.c

64

drm_gem_fb_get_obj(struct drm_framebuffer *fb, unsigned int plane)

sys/dev/pci/drm/drm_gem_framebuffer_helper.c

66

if (plane < nitems(fb->obj))

sys/dev/pci/drm/drm_gem_framebuffer_helper.c

67

return fb->obj[plane];

sys/dev/pci/drm/drm_mode_config.c

195

struct drm_plane *plane;

sys/dev/pci/drm/drm_mode_config.c

200

drm_for_each_plane(plane, dev)

sys/dev/pci/drm/drm_mode_config.c

201

if (plane->funcs->reset)

sys/dev/pci/drm/drm_mode_config.c

202

plane->funcs->reset(plane);

sys/dev/pci/drm/drm_mode_config.c

519

struct drm_plane *plane, *plt;

sys/dev/pci/drm/drm_mode_config.c

549

list_for_each_entry_safe(plane, plt, &dev->mode_config.plane_list,

sys/dev/pci/drm/drm_mode_config.c

551

plane->funcs->destroy(plane);

sys/dev/pci/drm/drm_mode_config.c

662

struct drm_plane *plane;

sys/dev/pci/drm/drm_mode_config.c

713

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_mode_config.c

714

if (plane->type == DRM_PLANE_TYPE_PRIMARY)

sys/dev/pci/drm/drm_modeset_lock.c

460

struct drm_plane *plane;

sys/dev/pci/drm/drm_modeset_lock.c

473

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_modeset_lock.c

474

ret = drm_modeset_lock(&plane->mutex, ctx);

sys/dev/pci/drm/drm_panic.c

1011

struct drm_plane *plane;

sys/dev/pci/drm/drm_panic.c

1016

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_panic.c

1017

if (!plane->helper_private || !plane->helper_private->get_scanout_buffer)

sys/dev/pci/drm/drm_panic.c

1019

kmsg_dump_unregister(&plane->kmsg_panic);

sys/dev/pci/drm/drm_panic.c

874

static void draw_panic_plane(struct drm_plane *plane, const char *description)

sys/dev/pci/drm/drm_panic.c

880

if (!drm_panic_trylock(plane->dev, flags))

sys/dev/pci/drm/drm_panic.c

883

ret = plane->helper_private->get_scanout_buffer(plane, &sb);

sys/dev/pci/drm/drm_panic.c

895

if (plane->helper_private->panic_flush)

sys/dev/pci/drm/drm_panic.c

896

plane->helper_private->panic_flush(plane);

sys/dev/pci/drm/drm_panic.c

901

drm_panic_unlock(plane->dev, flags);

sys/dev/pci/drm/drm_panic.c

911

struct drm_plane *plane = to_drm_plane(dumper);

sys/dev/pci/drm/drm_panic.c

914

draw_panic_plane(plane, detail->description);

sys/dev/pci/drm/drm_panic.c

932

struct drm_plane *plane = file->private_data;

sys/dev/pci/drm/drm_panic.c

934

draw_panic_plane(plane, "Test from debugfs");

sys/dev/pci/drm/drm_panic.c

945

static void debugfs_register_plane(struct drm_plane *plane, int index)

sys/dev/pci/drm/drm_panic.c

950

debugfs_create_file(fname, 0200, plane->dev->debugfs_root,

sys/dev/pci/drm/drm_panic.c

951

plane, &dbg_drm_panic_ops);

sys/dev/pci/drm/drm_panic.c

954

static void debugfs_register_plane(struct drm_plane *plane, int index) {}

sys/dev/pci/drm/drm_panic.c

965

struct drm_plane *plane;

sys/dev/pci/drm/drm_panic.c

970

drm_for_each_plane(plane, dev)

sys/dev/pci/drm/drm_panic.c

971

if (plane->helper_private && plane->helper_private->get_scanout_buffer)

sys/dev/pci/drm/drm_panic.c

983

struct drm_plane *plane;

sys/dev/pci/drm/drm_panic.c

989

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_panic.c

990

if (!plane->helper_private || !plane->helper_private->get_scanout_buffer)

sys/dev/pci/drm/drm_panic.c

992

plane->kmsg_panic.dump = drm_panic;

sys/dev/pci/drm/drm_panic.c

993

plane->kmsg_panic.max_reason = KMSG_DUMP_PANIC;

sys/dev/pci/drm/drm_panic.c

994

if (kmsg_dump_register(&plane->kmsg_panic))

sys/dev/pci/drm/drm_panic.c

997

debugfs_register_plane(plane, registered_plane);

sys/dev/pci/drm/drm_plane.c

1001

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_plane.c

1002

if (drm_plane_has_format(plane, format, modifier))

sys/dev/pci/drm/drm_plane.c

1018

static int __setplane_internal(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

1030

WARN_ON(drm_drv_uses_atomic_modeset(plane->dev));

sys/dev/pci/drm/drm_plane.c

1034

plane->old_fb = plane->fb;

sys/dev/pci/drm/drm_plane.c

1035

ret = plane->funcs->disable_plane(plane, ctx);

sys/dev/pci/drm/drm_plane.c

1037

plane->crtc = NULL;

sys/dev/pci/drm/drm_plane.c

1038

plane->fb = NULL;

sys/dev/pci/drm/drm_plane.c

1040

plane->old_fb = NULL;

sys/dev/pci/drm/drm_plane.c

1045

ret = __setplane_check(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1051

plane->old_fb = plane->fb;

sys/dev/pci/drm/drm_plane.c

1052

ret = plane->funcs->update_plane(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1056

plane->crtc = crtc;

sys/dev/pci/drm/drm_plane.c

1057

plane->fb = fb;

sys/dev/pci/drm/drm_plane.c

1058

drm_framebuffer_get(plane->fb);

sys/dev/pci/drm/drm_plane.c

1060

plane->old_fb = NULL;

sys/dev/pci/drm/drm_plane.c

1064

if (plane->old_fb)

sys/dev/pci/drm/drm_plane.c

1065

drm_framebuffer_put(plane->old_fb);

sys/dev/pci/drm/drm_plane.c

1066

plane->old_fb = NULL;

sys/dev/pci/drm/drm_plane.c

1071

static int __setplane_atomic(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

1082

WARN_ON(!drm_drv_uses_atomic_modeset(plane->dev));

sys/dev/pci/drm/drm_plane.c

1086

return plane->funcs->disable_plane(plane, ctx);

sys/dev/pci/drm/drm_plane.c

1095

ret = __setplane_check(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1101

return plane->funcs->update_plane(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1106

static int setplane_internal(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

1118

DRM_MODESET_LOCK_ALL_BEGIN(plane->dev, ctx,

sys/dev/pci/drm/drm_plane.c

1121

if (drm_drv_uses_atomic_modeset(plane->dev))

sys/dev/pci/drm/drm_plane.c

1122

ret = __setplane_atomic(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1126

ret = __setplane_internal(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1130

DRM_MODESET_LOCK_ALL_END(plane->dev, ctx, ret);

sys/dev/pci/drm/drm_plane.c

1139

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

1151

plane = drm_plane_find(dev, file_priv, plane_req->plane_id);

sys/dev/pci/drm/drm_plane.c

1152

if (!plane) {

sys/dev/pci/drm/drm_plane.c

1175

ret = setplane_internal(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1193

struct drm_plane *plane = crtc->cursor;

sys/dev/pci/drm/drm_plane.c

1207

BUG_ON(!plane);

sys/dev/pci/drm/drm_plane.c

1208

WARN_ON(plane->crtc != crtc && plane->crtc != NULL);

sys/dev/pci/drm/drm_plane.c

1223

if (plane->hotspot_x_property && plane->state)

sys/dev/pci/drm/drm_plane.c

1224

plane->state->hotspot_x = req->hot_x;

sys/dev/pci/drm/drm_plane.c

1225

if (plane->hotspot_y_property && plane->state)

sys/dev/pci/drm/drm_plane.c

1226

plane->state->hotspot_y = req->hot_y;

sys/dev/pci/drm/drm_plane.c

1231

if (plane->state)

sys/dev/pci/drm/drm_plane.c

1232

fb = plane->state->fb;

sys/dev/pci/drm/drm_plane.c

1234

fb = plane->fb;

sys/dev/pci/drm/drm_plane.c

1256

ret = __setplane_atomic(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1260

ret = __setplane_internal(plane, crtc, fb,

sys/dev/pci/drm/drm_plane.c

1386

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

1415

plane = crtc->primary;

sys/dev/pci/drm/drm_plane.c

1417

if (!drm_lease_held(file_priv, plane->base.id))

sys/dev/pci/drm/drm_plane.c

1464

ret = drm_modeset_lock(&plane->mutex, &ctx);

sys/dev/pci/drm/drm_plane.c

1468

if (plane->state)

sys/dev/pci/drm/drm_plane.c

1469

old_fb = plane->state->fb;

sys/dev/pci/drm/drm_plane.c

1471

old_fb = plane->fb;

sys/dev/pci/drm/drm_plane.c

1488

if (plane->state) {

sys/dev/pci/drm/drm_plane.c

1489

const struct drm_plane_state *state = plane->state;

sys/dev/pci/drm/drm_plane.c

1536

plane->old_fb = plane->fb;

sys/dev/pci/drm/drm_plane.c

1549

plane->old_fb = NULL;

sys/dev/pci/drm/drm_plane.c

1551

if (!plane->state) {

sys/dev/pci/drm/drm_plane.c

1552

plane->fb = fb;

sys/dev/pci/drm/drm_plane.c

1561

if (plane->old_fb)

sys/dev/pci/drm/drm_plane.c

1562

drm_framebuffer_put(plane->old_fb);

sys/dev/pci/drm/drm_plane.c

1563

plane->old_fb = NULL;

sys/dev/pci/drm/drm_plane.c

1654

void drm_plane_enable_fb_damage_clips(struct drm_plane *plane)

sys/dev/pci/drm/drm_plane.c

1656

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_plane.c

1659

drm_object_attach_property(&plane->base, config->prop_fb_damage_clips,

sys/dev/pci/drm/drm_plane.c

1702

struct drm_device *dev = state->plane->dev;

sys/dev/pci/drm/drm_plane.c

1706

if (!drm_mode_obj_find_prop_id(&state->plane->base,

sys/dev/pci/drm/drm_plane.c

1770

int drm_plane_create_scaling_filter_property(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

1774

drm_create_scaling_filter_prop(plane->dev, supported_filters);

sys/dev/pci/drm/drm_plane.c

1779

drm_object_attach_property(&plane->base, prop,

sys/dev/pci/drm/drm_plane.c

1781

plane->scaling_filter_property = prop;

sys/dev/pci/drm/drm_plane.c

1799

int drm_plane_add_size_hints_property(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

1803

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_plane.c

1808

if (drm_WARN_ON(dev, plane->type != DRM_PLANE_TYPE_CURSOR))

sys/dev/pci/drm/drm_plane.c

1817

drm_object_attach_property(&plane->base, config->size_hints_property,

sys/dev/pci/drm/drm_plane.c

198

struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

200

(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

210

formats_size = sizeof(__u32) * plane->format_count;

sys/dev/pci/drm/drm_plane.c

217

sizeof(struct drm_format_modifier) * plane->modifier_count;

sys/dev/pci/drm/drm_plane.c

233

blob_data->count_formats = plane->format_count;

sys/dev/pci/drm/drm_plane.c

235

blob_data->count_modifiers = plane->modifier_count;

sys/dev/pci/drm/drm_plane.c

240

memcpy(formats_ptr(blob_data), plane->format_types, formats_size);

sys/dev/pci/drm/drm_plane.c

243

for (i = 0; i < plane->modifier_count; i++) {

sys/dev/pci/drm/drm_plane.c

244

for (j = 0; j < plane->format_count; j++) {

sys/dev/pci/drm/drm_plane.c

246

format_mod_supported(plane,

sys/dev/pci/drm/drm_plane.c

247

plane->format_types[j],

sys/dev/pci/drm/drm_plane.c

248

plane->modifiers[i])) {

sys/dev/pci/drm/drm_plane.c

253

mod->modifier = plane->modifiers[i];

sys/dev/pci/drm/drm_plane.c

330

static int drm_plane_create_hotspot_properties(struct drm_plane *plane)

sys/dev/pci/drm/drm_plane.c

335

drm_WARN_ON(plane->dev,

sys/dev/pci/drm/drm_plane.c

336

!drm_core_check_feature(plane->dev,

sys/dev/pci/drm/drm_plane.c

339

prop_x = drm_property_create_signed_range(plane->dev, 0, "HOTSPOT_X",

sys/dev/pci/drm/drm_plane.c

344

prop_y = drm_property_create_signed_range(plane->dev, 0, "HOTSPOT_Y",

sys/dev/pci/drm/drm_plane.c

347

drm_property_destroy(plane->dev, prop_x);

sys/dev/pci/drm/drm_plane.c

351

drm_object_attach_property(&plane->base, prop_x, 0);

sys/dev/pci/drm/drm_plane.c

352

drm_object_attach_property(&plane->base, prop_y, 0);

sys/dev/pci/drm/drm_plane.c

353

plane->hotspot_x_property = prop_x;

sys/dev/pci/drm/drm_plane.c

354

plane->hotspot_y_property = prop_y;

sys/dev/pci/drm/drm_plane.c

361

struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

393

ret = drm_mode_object_add(dev, &plane->base, DRM_MODE_OBJECT_PLANE);

sys/dev/pci/drm/drm_plane.c

397

drm_modeset_lock_init(&plane->mutex);

sys/dev/pci/drm/drm_plane.c

399

plane->base.properties = &plane->properties;

sys/dev/pci/drm/drm_plane.c

400

plane->dev = dev;

sys/dev/pci/drm/drm_plane.c

401

plane->funcs = funcs;

sys/dev/pci/drm/drm_plane.c

402

plane->format_types = kmalloc_array(format_count, sizeof(uint32_t),

sys/dev/pci/drm/drm_plane.c

404

if (!plane->format_types) {

sys/dev/pci/drm/drm_plane.c

406

drm_mode_object_unregister(dev, &plane->base);

sys/dev/pci/drm/drm_plane.c

426

plane->modifier_count = format_modifier_count;

sys/dev/pci/drm/drm_plane.c

427

plane->modifiers = kmalloc_array(format_modifier_count,

sys/dev/pci/drm/drm_plane.c

431

if (format_modifier_count && !plane->modifiers) {

sys/dev/pci/drm/drm_plane.c

433

kfree(plane->format_types);

sys/dev/pci/drm/drm_plane.c

434

drm_mode_object_unregister(dev, &plane->base);

sys/dev/pci/drm/drm_plane.c

439

plane->name = kvasprintf(GFP_KERNEL, name, ap);

sys/dev/pci/drm/drm_plane.c

441

plane->name = kasprintf(GFP_KERNEL, "plane-%d",

sys/dev/pci/drm/drm_plane.c

444

if (!plane->name) {

sys/dev/pci/drm/drm_plane.c

445

kfree(plane->format_types);

sys/dev/pci/drm/drm_plane.c

446

kfree(plane->modifiers);

sys/dev/pci/drm/drm_plane.c

447

drm_mode_object_unregister(dev, &plane->base);

sys/dev/pci/drm/drm_plane.c

451

memcpy(plane->format_types, formats, format_count * sizeof(uint32_t));

sys/dev/pci/drm/drm_plane.c

452

plane->format_count = format_count;

sys/dev/pci/drm/drm_plane.c

453

memcpy(plane->modifiers, format_modifiers,

sys/dev/pci/drm/drm_plane.c

455

plane->possible_crtcs = possible_crtcs;

sys/dev/pci/drm/drm_plane.c

456

plane->type = type;

sys/dev/pci/drm/drm_plane.c

458

list_add_tail(&plane->head, &config->plane_list);

sys/dev/pci/drm/drm_plane.c

459

plane->index = config->num_total_plane++;

sys/dev/pci/drm/drm_plane.c

461

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/drm_plane.c

463

plane->type);

sys/dev/pci/drm/drm_plane.c

466

drm_object_attach_property(&plane->base, config->prop_fb_id, 0);

sys/dev/pci/drm/drm_plane.c

467

drm_object_attach_property(&plane->base, config->prop_in_fence_fd, -1);

sys/dev/pci/drm/drm_plane.c

468

drm_object_attach_property(&plane->base, config->prop_crtc_id, 0);

sys/dev/pci/drm/drm_plane.c

469

drm_object_attach_property(&plane->base, config->prop_crtc_x, 0);

sys/dev/pci/drm/drm_plane.c

470

drm_object_attach_property(&plane->base, config->prop_crtc_y, 0);

sys/dev/pci/drm/drm_plane.c

471

drm_object_attach_property(&plane->base, config->prop_crtc_w, 0);

sys/dev/pci/drm/drm_plane.c

472

drm_object_attach_property(&plane->base, config->prop_crtc_h, 0);

sys/dev/pci/drm/drm_plane.c

473

drm_object_attach_property(&plane->base, config->prop_src_x, 0);

sys/dev/pci/drm/drm_plane.c

474

drm_object_attach_property(&plane->base, config->prop_src_y, 0);

sys/dev/pci/drm/drm_plane.c

475

drm_object_attach_property(&plane->base, config->prop_src_w, 0);

sys/dev/pci/drm/drm_plane.c

476

drm_object_attach_property(&plane->base, config->prop_src_h, 0);

sys/dev/pci/drm/drm_plane.c

480

drm_plane_create_hotspot_properties(plane);

sys/dev/pci/drm/drm_plane.c

484

blob = create_in_format_blob(dev, plane,

sys/dev/pci/drm/drm_plane.c

485

plane->funcs->format_mod_supported);

sys/dev/pci/drm/drm_plane.c

487

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/drm_plane.c

492

if (plane->funcs->format_mod_supported_async) {

sys/dev/pci/drm/drm_plane.c

493

blob = create_in_format_blob(dev, plane,

sys/dev/pci/drm/drm_plane.c

494

plane->funcs->format_mod_supported_async);

sys/dev/pci/drm/drm_plane.c

496

drm_object_attach_property(&plane->base,

sys/dev/pci/drm/drm_plane.c

532

int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

546

ret = __drm_universal_plane_init(dev, plane, possible_crtcs, funcs,

sys/dev/pci/drm/drm_plane.c

556

struct drm_plane *plane = ptr;

sys/dev/pci/drm/drm_plane.c

558

if (WARN_ON(!plane->dev))

sys/dev/pci/drm/drm_plane.c

561

drm_plane_cleanup(plane);

sys/dev/pci/drm/drm_plane.c

573

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

584

plane = container + offset;

sys/dev/pci/drm/drm_plane.c

587

ret = __drm_universal_plane_init(dev, plane, possible_crtcs, funcs,

sys/dev/pci/drm/drm_plane.c

595

plane);

sys/dev/pci/drm/drm_plane.c

612

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

623

plane = container + offset;

sys/dev/pci/drm/drm_plane.c

626

ret = __drm_universal_plane_init(dev, plane, possible_crtcs, funcs,

sys/dev/pci/drm/drm_plane.c

645

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

648

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_plane.c

649

if (plane->funcs->late_register)

sys/dev/pci/drm/drm_plane.c

650

ret = plane->funcs->late_register(plane);

sys/dev/pci/drm/drm_plane.c

654

if (plane->zpos_property)

sys/dev/pci/drm/drm_plane.c

667

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

669

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_plane.c

670

if (plane->funcs->early_unregister)

sys/dev/pci/drm/drm_plane.c

671

plane->funcs->early_unregister(plane);

sys/dev/pci/drm/drm_plane.c

683

void drm_plane_cleanup(struct drm_plane *plane)

sys/dev/pci/drm/drm_plane.c

685

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_plane.c

687

drm_modeset_lock_fini(&plane->mutex);

sys/dev/pci/drm/drm_plane.c

689

kfree(plane->format_types);

sys/dev/pci/drm/drm_plane.c

690

kfree(plane->modifiers);

sys/dev/pci/drm/drm_plane.c

691

drm_mode_object_unregister(dev, &plane->base);

sys/dev/pci/drm/drm_plane.c

693

BUG_ON(list_empty(&plane->head));

sys/dev/pci/drm/drm_plane.c

700

list_del(&plane->head);

sys/dev/pci/drm/drm_plane.c

703

WARN_ON(plane->state && !plane->funcs->atomic_destroy_state);

sys/dev/pci/drm/drm_plane.c

704

if (plane->state && plane->funcs->atomic_destroy_state)

sys/dev/pci/drm/drm_plane.c

705

plane->funcs->atomic_destroy_state(plane, plane->state);

sys/dev/pci/drm/drm_plane.c

707

kfree(plane->name);

sys/dev/pci/drm/drm_plane.c

709

memset(plane, 0, sizeof(*plane));

sys/dev/pci/drm/drm_plane.c

724

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

726

drm_for_each_plane(plane, dev)

sys/dev/pci/drm/drm_plane.c

727

if (idx == plane->index)

sys/dev/pci/drm/drm_plane.c

728

return plane;

sys/dev/pci/drm/drm_plane.c

749

void drm_plane_force_disable(struct drm_plane *plane)

sys/dev/pci/drm/drm_plane.c

753

if (!plane->fb)

sys/dev/pci/drm/drm_plane.c

756

WARN_ON(drm_drv_uses_atomic_modeset(plane->dev));

sys/dev/pci/drm/drm_plane.c

758

plane->old_fb = plane->fb;

sys/dev/pci/drm/drm_plane.c

759

ret = plane->funcs->disable_plane(plane, NULL);

sys/dev/pci/drm/drm_plane.c

762

plane->old_fb = NULL;

sys/dev/pci/drm/drm_plane.c

766

drm_framebuffer_put(plane->old_fb);

sys/dev/pci/drm/drm_plane.c

767

plane->old_fb = NULL;

sys/dev/pci/drm/drm_plane.c

768

plane->fb = NULL;

sys/dev/pci/drm/drm_plane.c

769

plane->crtc = NULL;

sys/dev/pci/drm/drm_plane.c

786

int drm_mode_plane_set_obj_prop(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

791

struct drm_mode_object *obj = &plane->base;

sys/dev/pci/drm/drm_plane.c

793

if (plane->funcs->set_property)

sys/dev/pci/drm/drm_plane.c

794

ret = plane->funcs->set_property(plane, property, value);

sys/dev/pci/drm/drm_plane.c

806

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

819

drm_for_each_plane(plane, dev) {

sys/dev/pci/drm/drm_plane.c

824

if (plane->type != DRM_PLANE_TYPE_OVERLAY &&

sys/dev/pci/drm/drm_plane.c

835

if (plane->type == DRM_PLANE_TYPE_CURSOR &&

sys/dev/pci/drm/drm_plane.c

841

if (drm_lease_held(file_priv, plane->base.id)) {

sys/dev/pci/drm/drm_plane.c

843

put_user(plane->base.id, plane_ptr + count))

sys/dev/pci/drm/drm_plane.c

857

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane.c

863

plane = drm_plane_find(dev, file_priv, plane_resp->plane_id);

sys/dev/pci/drm/drm_plane.c

864

if (!plane)

sys/dev/pci/drm/drm_plane.c

867

drm_modeset_lock(&plane->mutex, NULL);

sys/dev/pci/drm/drm_plane.c

868

if (plane->state && plane->state->crtc && drm_lease_held(file_priv, plane->state->crtc->base.id))

sys/dev/pci/drm/drm_plane.c

869

plane_resp->crtc_id = plane->state->crtc->base.id;

sys/dev/pci/drm/drm_plane.c

870

else if (!plane->state && plane->crtc && drm_lease_held(file_priv, plane->crtc->base.id))

sys/dev/pci/drm/drm_plane.c

871

plane_resp->crtc_id = plane->crtc->base.id;

sys/dev/pci/drm/drm_plane.c

875

if (plane->state && plane->state->fb)

sys/dev/pci/drm/drm_plane.c

876

plane_resp->fb_id = plane->state->fb->base.id;

sys/dev/pci/drm/drm_plane.c

877

else if (!plane->state && plane->fb)

sys/dev/pci/drm/drm_plane.c

878

plane_resp->fb_id = plane->fb->base.id;

sys/dev/pci/drm/drm_plane.c

881

drm_modeset_unlock(&plane->mutex);

sys/dev/pci/drm/drm_plane.c

883

plane_resp->plane_id = plane->base.id;

sys/dev/pci/drm/drm_plane.c

885

plane->possible_crtcs);

sys/dev/pci/drm/drm_plane.c

893

if (plane->format_count &&

sys/dev/pci/drm/drm_plane.c

894

(plane_resp->count_format_types >= plane->format_count)) {

sys/dev/pci/drm/drm_plane.c

897

plane->format_types,

sys/dev/pci/drm/drm_plane.c

898

sizeof(uint32_t) * plane->format_count)) {

sys/dev/pci/drm/drm_plane.c

902

plane_resp->count_format_types = plane->format_count;

sys/dev/pci/drm/drm_plane.c

916

bool drm_plane_has_format(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

921

for (i = 0; i < plane->format_count; i++) {

sys/dev/pci/drm/drm_plane.c

922

if (format == plane->format_types[i])

sys/dev/pci/drm/drm_plane.c

925

if (i == plane->format_count)

sys/dev/pci/drm/drm_plane.c

928

if (plane->funcs->format_mod_supported) {

sys/dev/pci/drm/drm_plane.c

929

if (!plane->funcs->format_mod_supported(plane, format, modifier))

sys/dev/pci/drm/drm_plane.c

932

if (!plane->modifier_count)

sys/dev/pci/drm/drm_plane.c

935

for (i = 0; i < plane->modifier_count; i++) {

sys/dev/pci/drm/drm_plane.c

936

if (modifier == plane->modifiers[i])

sys/dev/pci/drm/drm_plane.c

939

if (i == plane->modifier_count)

sys/dev/pci/drm/drm_plane.c

947

static int __setplane_check(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane.c

958

if (!(plane->possible_crtcs & drm_crtc_mask(crtc))) {

sys/dev/pci/drm/drm_plane.c

964

if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) {

sys/dev/pci/drm/drm_plane.c

999

struct drm_plane *plane;

sys/dev/pci/drm/drm_plane_helper.c

108

.plane = plane,

sys/dev/pci/drm/drm_plane_helper.c

165

int drm_plane_helper_update_primary(struct drm_plane *plane, struct drm_crtc *crtc,

sys/dev/pci/drm/drm_plane_helper.c

192

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_plane_helper.c

200

ret = drm_plane_helper_check_update(plane, crtc, fb,

sys/dev/pci/drm/drm_plane_helper.c

215

return plane->funcs->disable_plane(plane, ctx);

sys/dev/pci/drm/drm_plane_helper.c

258

int drm_plane_helper_disable_primary(struct drm_plane *plane,

sys/dev/pci/drm/drm_plane_helper.c

261

struct drm_device *dev = plane->dev;

sys/dev/pci/drm/drm_plane_helper.c

277

void drm_plane_helper_destroy(struct drm_plane *plane)

sys/dev/pci/drm/drm_plane_helper.c

279

drm_plane_cleanup(plane);

sys/dev/pci/drm/drm_plane_helper.c

280

kfree(plane);

sys/dev/pci/drm/drm_plane_helper.c

95

static int drm_plane_helper_check_update(struct drm_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1003

plane->max_stride = i965_plane_max_stride;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1005

plane->max_stride = i915_plane_max_stride;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1007

plane->max_stride = i8xx_plane_max_stride;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1010

plane->max_stride = hsw_primary_max_stride;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1012

plane->max_stride = ilk_primary_max_stride;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1016

plane->min_alignment = vlv_plane_min_alignment;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1018

plane->min_alignment = g4x_primary_min_alignment;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1020

plane->min_alignment = i965_plane_min_alignment;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1022

plane->min_alignment = i9xx_plane_min_alignment;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1026

plane->vtd_guard = 128;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1029

plane->update_arm = i830_plane_update_arm;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1031

plane->update_noarm = i9xx_plane_update_noarm;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1032

plane->update_arm = i9xx_plane_update_arm;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1034

plane->disable_arm = i9xx_plane_disable_arm;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1035

plane->get_hw_state = i9xx_plane_get_hw_state;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1036

plane->check_plane = i9xx_plane_check;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1039

plane->surf_offset = i965_plane_surf_offset;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1041

plane->surf_offset = i8xx_plane_surf_offset;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1044

plane->capture_error = g4x_primary_capture_error;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1046

plane->capture_error = i965_plane_capture_error;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1048

plane->capture_error = i8xx_plane_capture_error;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1052

plane->async_flip = vlv_primary_async_flip;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1053

plane->enable_flip_done = vlv_primary_enable_flip_done;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1054

plane->disable_flip_done = vlv_primary_disable_flip_done;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1055

plane->can_async_flip = i9xx_plane_can_async_flip;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1057

plane->need_async_flip_toggle_wa = true;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1058

plane->async_flip = g4x_primary_async_flip;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1059

plane->enable_flip_done = bdw_primary_enable_flip_done;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1060

plane->disable_flip_done = bdw_primary_disable_flip_done;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1061

plane->can_async_flip = i9xx_plane_can_async_flip;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1063

plane->async_flip = g4x_primary_async_flip;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1064

plane->enable_flip_done = ivb_primary_enable_flip_done;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1065

plane->disable_flip_done = ivb_primary_disable_flip_done;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1066

plane->can_async_flip = i9xx_plane_can_async_flip;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1068

plane->async_flip = g4x_primary_async_flip;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1069

plane->enable_flip_done = ilk_primary_enable_flip_done;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1070

plane->disable_flip_done = ilk_primary_disable_flip_done;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1071

plane->can_async_flip = i9xx_plane_can_async_flip;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1075

plane->disable_tiling = i9xx_disable_tiling;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1080

ret = drm_universal_plane_init(display->drm, &plane->base,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1087

ret = drm_universal_plane_init(display->drm, &plane->base,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1093

plane_name(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1112

drm_plane_create_rotation_property(&plane->base,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1117

drm_plane_create_zpos_immutable_property(&plane->base, zpos);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1119

intel_plane_helper_add(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1121

return plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1124

intel_plane_free(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1167

struct intel_plane *plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1168

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1176

if (!plane->get_hw_state(plane, &pipe))

sys/dev/pci/drm/i915/display/i9xx_plane.c

1245

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1256

struct intel_plane *plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1258

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/i9xx_plane.c

1259

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

142

static bool i9xx_plane_has_windowing(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

144

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

145

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

232

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

253

plane->base.base.id, plane->base.name, src_w);

sys/dev/pci/drm/i915/display/i9xx_plane.c

277

unsigned int alignment = plane->min_alignment(plane, fb, 0);

sys/dev/pci/drm/i915/display/i9xx_plane.c

284

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/i9xx_plane.c

332

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

342

i9xx_plane_has_windowing(plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

441

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

445

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

446

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

470

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

474

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

475

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

483

if (plane->need_async_flip_toggle_wa &&

sys/dev/pci/drm/i915/display/i9xx_plane.c

484

crtc_state->async_flip_planes & BIT(plane->id))

sys/dev/pci/drm/i915/display/i9xx_plane.c

525

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

535

i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/i9xx_plane.c

536

i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/i9xx_plane.c

540

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

543

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

544

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

568

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

571

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

572

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

580

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

583

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

584

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

591

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

594

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

595

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

603

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

608

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

610

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

621

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

626

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

627

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

633

bdw_primary_enable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

635

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

636

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

644

bdw_primary_disable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

646

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

647

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

655

ivb_primary_enable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

657

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

660

ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

665

ivb_primary_disable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

667

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

670

ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

675

ilk_primary_enable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

677

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

680

ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

685

ilk_primary_disable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

687

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

690

ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

695

vlv_primary_enable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

697

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

698

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

706

vlv_primary_disable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

708

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

709

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

721

static bool i9xx_plane_get_hw_state(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

724

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

726

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

736

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_plane.c

746

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

756

hsw_primary_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

768

ilk_primary_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

783

i965_plane_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

798

i915_plane_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

809

i8xx_plane_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

813

if (plane->i9xx_plane == PLANE_C)

sys/dev/pci/drm/i915/display/i9xx_plane.c

819

unsigned int vlv_plane_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

823

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

825

if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))

sys/dev/pci/drm/i915/display/i9xx_plane.c

843

static unsigned int g4x_primary_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

847

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

849

if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))

sys/dev/pci/drm/i915/display/i9xx_plane.c

865

static unsigned int i965_plane_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

880

static unsigned int i9xx_plane_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.c

907

static void i9xx_disable_tiling(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/i9xx_plane.c

909

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

910

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

931

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

939

plane = intel_plane_alloc();

sys/dev/pci/drm/i915/display/i9xx_plane.c

940

if (IS_ERR(plane))

sys/dev/pci/drm/i915/display/i9xx_plane.c

941

return plane;

sys/dev/pci/drm/i915/display/i9xx_plane.c

943

plane->pipe = pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

950

plane->i9xx_plane = (enum i9xx_plane_id) !pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

952

plane->i9xx_plane = (enum i9xx_plane_id) pipe;

sys/dev/pci/drm/i915/display/i9xx_plane.c

953

plane->id = PLANE_PRIMARY;

sys/dev/pci/drm/i915/display/i9xx_plane.c

954

plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);

sys/dev/pci/drm/i915/display/i9xx_plane.c

956

intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane);

sys/dev/pci/drm/i915/display/i9xx_plane.c

993

plane->min_cdclk = vlv_plane_min_cdclk;

sys/dev/pci/drm/i915/display/i9xx_plane.c

995

plane->min_cdclk = hsw_plane_min_cdclk;

sys/dev/pci/drm/i915/display/i9xx_plane.c

997

plane->min_cdclk = ivb_plane_min_cdclk;

sys/dev/pci/drm/i915/display/i9xx_plane.c

999

plane->min_cdclk = i9xx_plane_min_cdclk;

sys/dev/pci/drm/i915/display/i9xx_plane.h

20

unsigned int i965_plane_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.h

23

unsigned int vlv_plane_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane.h

37

static inline unsigned int i965_plane_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

100

#define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

107

#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

12

#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

15

#define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

49

#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

52

#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

55

#define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

58

#define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

65

#define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

72

#define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

76

#define DSPTILEOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

83

#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

86

#define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

89

#define DSPGAMC(dev_priv, plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */

sys/dev/pci/drm/i915/display/i9xx_plane_regs.h

93

#define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1001

if (plane->id == PLANE_CURSOR) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

1003

} else if (plane->id == PLANE_PRIMARY &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

1015

wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),

sys/dev/pci/drm/i915/display/i9xx_wm.c

1032

dirty |= raw->plane[plane_id] != value;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1033

raw->plane[plane_id] = value;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1066

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1067

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1088

dirty |= raw->plane[plane_id] != wm;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1089

raw->plane[plane_id] = wm;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1096

raw->plane[plane_id]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1120

plane->base.name,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1121

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1122

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1123

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1140

return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1164

wm_state->wm.plane[plane_id] = USHRT_MAX;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1170

wm_state->sr.plane = USHRT_MAX;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1177

wm_state->hpll.plane = USHRT_MAX;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1214

wm_state->wm.plane[plane_id] = raw->plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1221

wm_state->sr.plane = raw->plane[PLANE_PRIMARY];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1222

wm_state->sr.cursor = raw->plane[PLANE_CURSOR];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1232

wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1233

wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1266

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1270

for_each_oldnew_intel_plane_in_state(state, plane,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1278

dirty |= BIT(plane->id);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1316

intermediate->wm.plane[plane_id] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

1317

max(optimal->wm.plane[plane_id],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1318

active->wm.plane[plane_id]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1320

drm_WARN_ON(display->drm, intermediate->wm.plane[plane_id] >

sys/dev/pci/drm/i915/display/i9xx_wm.c

1324

intermediate->sr.plane = max(optimal->sr.plane,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1325

active->sr.plane);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1331

intermediate->hpll.plane = max(optimal->hpll.plane,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1332

active->hpll.plane);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1339

(intermediate->sr.plane >

sys/dev/pci/drm/i915/display/i9xx_wm.c

1345

(intermediate->sr.plane >

sys/dev/pci/drm/i915/display/i9xx_wm.c

1515

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1531

if (plane->id == PLANE_CURSOR) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

157

#define FW_WM(value, plane) \

sys/dev/pci/drm/i915/display/i9xx_wm.c

1579

total_rate = raw->plane[PLANE_PRIMARY] +

sys/dev/pci/drm/i915/display/i9xx_wm.c

158

(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1580

raw->plane[PLANE_SPRITE0] +

sys/dev/pci/drm/i915/display/i9xx_wm.c

1581

raw->plane[PLANE_SPRITE1] +

sys/dev/pci/drm/i915/display/i9xx_wm.c

1594

fifo_state->plane[plane_id] = 0;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1598

rate = raw->plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1599

fifo_state->plane[plane_id] = fifo_size * rate / total_rate;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1600

fifo_left -= fifo_state->plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1603

fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1606

fifo_state->plane[PLANE_CURSOR] = 63;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1621

fifo_state->plane[plane_id] += plane_extra;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1630

fifo_state->plane[PLANE_PRIMARY] = fifo_left;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1646

wm_state->wm[level].plane[plane_id] = USHRT_MAX;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1649

wm_state->sr[level].plane = USHRT_MAX;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1674

dirty |= raw->plane[plane_id] != value;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1675

raw->plane[plane_id] = value;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1685

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1686

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1703

dirty |= raw->plane[plane_id] != wm;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1704

raw->plane[plane_id] = wm;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1714

plane->base.name,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1715

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1716

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1717

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1730

return raw->plane[plane_id] <= fifo_state->plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1770

wm_state->wm[level].plane[plane_id] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

1771

vlv_invert_wm_value(raw->plane[plane_id],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1772

fifo_state->plane[plane_id]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1775

wm_state->sr[level].plane =

sys/dev/pci/drm/i915/display/i9xx_wm.c

1776

vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1777

raw->plane[PLANE_SPRITE0],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1778

raw->plane[PLANE_SPRITE1]),

sys/dev/pci/drm/i915/display/i9xx_wm.c

1782

vlv_invert_wm_value(raw->plane[PLANE_CURSOR],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1805

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1809

for_each_oldnew_intel_plane_in_state(state, plane,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1817

dirty |= BIT(plane->id);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1858

#define VLV_FIFO(plane, value) \

sys/dev/pci/drm/i915/display/i9xx_wm.c

1859

(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1877

sprite0_start = fifo_state->plane[PLANE_PRIMARY];

sys/dev/pci/drm/i915/display/i9xx_wm.c

1878

sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1879

fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1881

drm_WARN_ON(display->drm, fifo_state->plane[PLANE_CURSOR] != 63);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1988

intermediate->wm[level].plane[plane_id] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

1989

min(optimal->wm[level].plane[plane_id],

sys/dev/pci/drm/i915/display/i9xx_wm.c

1990

active->wm[level].plane[plane_id]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1993

intermediate->sr[level].plane = min(optimal->sr[level].plane,

sys/dev/pci/drm/i915/display/i9xx_wm.c

1994

active->sr[level].plane);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2064

wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2065

wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2066

wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2067

wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2214

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2216

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2217

if (plane->id == PLANE_PRIMARY &&

sys/dev/pci/drm/i915/display/i9xx_wm.c

2218

plane->i9xx_plane == i9xx_plane)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2219

return intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2929

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2939

intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

2940

if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2942

else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)

sys/dev/pci/drm/i915/display/i9xx_wm.c

2944

else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)

sys/dev/pci/drm/i915/display/i9xx_wm.c

316

fifo_state->plane[PLANE_PRIMARY] = sprite0_start;

sys/dev/pci/drm/i915/display/i9xx_wm.c

317

fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;

sys/dev/pci/drm/i915/display/i9xx_wm.c

318

fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;

sys/dev/pci/drm/i915/display/i9xx_wm.c

319

fifo_state->plane[PLANE_CURSOR] = 63;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3540

struct drm_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3559

drm_for_each_plane(plane, state->dev) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3562

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3660

#define _FW_WM(value, plane) \

sys/dev/pci/drm/i915/display/i9xx_wm.c

3661

(((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3662

#define _FW_WM_VLV(value, plane) \

sys/dev/pci/drm/i915/display/i9xx_wm.c

3663

(((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)

sys/dev/pci/drm/i915/display/i9xx_wm.c

3671

wm->sr.plane = _FW_WM(tmp, SR);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3672

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3673

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3674

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3680

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3681

wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3682

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3688

wm->hpll.plane = _FW_WM(tmp, HPLL_SR);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3700

wm->ddl[pipe].plane[PLANE_PRIMARY] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3702

wm->ddl[pipe].plane[PLANE_CURSOR] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3704

wm->ddl[pipe].plane[PLANE_SPRITE0] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3706

wm->ddl[pipe].plane[PLANE_SPRITE1] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3711

wm->sr.plane = _FW_WM(tmp, SR);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3712

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3713

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3714

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3717

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3718

wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3719

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3726

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3727

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3730

wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3731

wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3734

wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3735

wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3738

wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3739

wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3740

wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3741

wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3742

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3743

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3744

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3745

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3746

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3747

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3750

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3751

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3754

wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3755

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3756

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3757

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3758

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3759

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3760

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3793

active->wm.plane[plane_id] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3794

wm->pipe[pipe].plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

3807

raw->plane[plane_id] = active->wm.plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

3814

raw->plane[PLANE_PRIMARY] = active->sr.plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3815

raw->plane[PLANE_CURSOR] = active->sr.cursor;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3816

raw->plane[PLANE_SPRITE0] = 0;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3824

raw->plane[PLANE_PRIMARY] = active->hpll.plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3825

raw->plane[PLANE_CURSOR] = active->hpll.cursor;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3826

raw->plane[PLANE_SPRITE0] = 0;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3844

wm->pipe[pipe].plane[PLANE_PRIMARY],

sys/dev/pci/drm/i915/display/i9xx_wm.c

3845

wm->pipe[pipe].plane[PLANE_CURSOR],

sys/dev/pci/drm/i915/display/i9xx_wm.c

3846

wm->pipe[pipe].plane[PLANE_SPRITE0]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3851

wm->sr.plane, wm->sr.cursor, wm->sr.fbc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3854

wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3862

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3867

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

3869

intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3873

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3874

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3884

raw->plane[plane_id] = 0;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3977

active->sr[level].plane = wm->sr.plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3981

active->wm[level].plane[plane_id] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3982

wm->pipe[pipe].plane[plane_id];

sys/dev/pci/drm/i915/display/i9xx_wm.c

3984

raw->plane[plane_id] =

sys/dev/pci/drm/i915/display/i9xx_wm.c

3985

vlv_invert_wm_value(active->wm[level].plane[plane_id],

sys/dev/pci/drm/i915/display/i9xx_wm.c

3986

fifo_state->plane[plane_id]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4001

wm->pipe[pipe].plane[PLANE_PRIMARY],

sys/dev/pci/drm/i915/display/i9xx_wm.c

4002

wm->pipe[pipe].plane[PLANE_CURSOR],

sys/dev/pci/drm/i915/display/i9xx_wm.c

4003

wm->pipe[pipe].plane[PLANE_SPRITE0],

sys/dev/pci/drm/i915/display/i9xx_wm.c

4004

wm->pipe[pipe].plane[PLANE_SPRITE1]);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4009

wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4014

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4019

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/i9xx_wm.c

4021

intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4025

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4026

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4036

raw->plane[plane_id] = 0;

sys/dev/pci/drm/i915/display/i9xx_wm.c

774

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/i9xx_wm.c

777

for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,

sys/dev/pci/drm/i915/display/i9xx_wm.c

779

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/i9xx_wm.c

814

FW_WM(wm->sr.plane, SR) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

815

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

816

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

817

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));

sys/dev/pci/drm/i915/display/i9xx_wm.c

822

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

823

FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

824

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));

sys/dev/pci/drm/i915/display/i9xx_wm.c

829

FW_WM(wm->hpll.plane, HPLL_SR));

sys/dev/pci/drm/i915/display/i9xx_wm.c

834

#define FW_WM_VLV(value, plane) \

sys/dev/pci/drm/i915/display/i9xx_wm.c

835

(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)

sys/dev/pci/drm/i915/display/i9xx_wm.c

846

(wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

847

(wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

848

(wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

849

(wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));

sys/dev/pci/drm/i915/display/i9xx_wm.c

864

FW_WM(wm->sr.plane, SR) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

865

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

866

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

867

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));

sys/dev/pci/drm/i915/display/i9xx_wm.c

869

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

870

FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

871

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));

sys/dev/pci/drm/i915/display/i9xx_wm.c

877

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

878

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

sys/dev/pci/drm/i915/display/i9xx_wm.c

880

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

881

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));

sys/dev/pci/drm/i915/display/i9xx_wm.c

883

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

884

FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));

sys/dev/pci/drm/i915/display/i9xx_wm.c

886

FW_WM(wm->sr.plane >> 9, SR_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

887

FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

888

FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

889

FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

890

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

891

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

892

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

893

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

894

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

895

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));

sys/dev/pci/drm/i915/display/i9xx_wm.c

898

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

899

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

sys/dev/pci/drm/i915/display/i9xx_wm.c

901

FW_WM(wm->sr.plane >> 9, SR_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

902

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

903

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

904

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

905

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

906

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |

sys/dev/pci/drm/i915/display/i9xx_wm.c

907

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));

sys/dev/pci/drm/i915/display/i9xx_wm.c

972

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/i9xx_wm.c

993

if (plane->id == PLANE_PRIMARY &&

sys/dev/pci/drm/i915/display/intel_cdclk.c

2817

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2820

for_each_intel_plane_on_crtc(display->drm, crtc, plane)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2821

min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3192

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3201

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3202

ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);

sys/dev/pci/drm/i915/display/intel_color.c

1066

struct intel_plane *plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/intel_color.c

1067

enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

sys/dev/pci/drm/i915/display/intel_color.c

1961

struct intel_plane *plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/intel_color.c

1964

plane->disable_arm(NULL, plane, crtc_state);

sys/dev/pci/drm/i915/display/intel_color.c

2136

static bool need_plane_update(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_color.c

2139

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_color.c

2146

return crtc_state->active_planes & BIT(plane->id) ||

sys/dev/pci/drm/i915/display/intel_color.c

2147

(DISPLAY_VER(display) < 9 && plane->id == PLANE_PRIMARY);

sys/dev/pci/drm/i915/display/intel_color.c

2159

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_color.c

2169

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_color.c

2172

if (!need_plane_update(plane, new_crtc_state))

sys/dev/pci/drm/i915/display/intel_color.c

2175

plane_state = intel_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_color.c

2179

new_crtc_state->update_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_crtc.c

333

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_crtc.c

336

plane = skl_universal_plane_create(display, pipe, PLANE_2 + sprite);

sys/dev/pci/drm/i915/display/intel_crtc.c

338

plane = intel_sprite_plane_create(display, pipe, sprite);

sys/dev/pci/drm/i915/display/intel_crtc.c

339

if (IS_ERR(plane)) {

sys/dev/pci/drm/i915/display/intel_crtc.c

340

ret = PTR_ERR(plane);

sys/dev/pci/drm/i915/display/intel_crtc.c

343

crtc->plane_ids_mask |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_crtc.c

541

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_crtc.c

545

for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,

sys/dev/pci/drm/i915/display/intel_crtc.c

695

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_crtc.c

699

for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

117

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

122

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

128

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

183

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

380

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

381

if (plane->pipe == crtc->pipe)

sys/dev/pci/drm/i915/display/intel_cursor.c

110

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_cursor.c

141

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

149

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_cursor.c

184

i845_cursor_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

191

static unsigned int i845_cursor_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

230

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

246

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_cursor.c

263

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_cursor.c

275

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

279

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

298

if (plane->cursor.base != base ||

sys/dev/pci/drm/i915/display/intel_cursor.c

299

plane->cursor.size != size ||

sys/dev/pci/drm/i915/display/intel_cursor.c

300

plane->cursor.cntl != cntl) {

sys/dev/pci/drm/i915/display/intel_cursor.c

307

plane->cursor.base = base;

sys/dev/pci/drm/i915/display/intel_cursor.c

308

plane->cursor.size = size;

sys/dev/pci/drm/i915/display/intel_cursor.c

309

plane->cursor.cntl = cntl;

sys/dev/pci/drm/i915/display/intel_cursor.c

316

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

319

i845_cursor_update_arm(dsb, plane, crtc_state, NULL);

sys/dev/pci/drm/i915/display/intel_cursor.c

322

static bool i845_cursor_get_hw_state(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

325

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

345

i9xx_cursor_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

349

return plane->base.dev->mode_config.cursor_width * 4;

sys/dev/pci/drm/i915/display/intel_cursor.c

352

static unsigned int i830_cursor_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

360

static unsigned int i85x_cursor_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

367

static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

371

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

474

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

476

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

491

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_cursor.c

504

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_cursor.c

523

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_cursor.c

533

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

536

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

537

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

546

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

550

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

553

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

565

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

569

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

570

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

587

wa_16021440873(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

589

i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

617

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

620

struct intel_display *display = to_intel_display(plane->base.dev);

sys/dev/pci/drm/i915/display/intel_cursor.c

621

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_cursor.c

622

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

650

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

654

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

655

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

693

skl_write_cursor_wm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

696

i9xx_cursor_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

698

i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

700

if (plane->cursor.base != base ||

sys/dev/pci/drm/i915/display/intel_cursor.c

701

plane->cursor.size != fbc_ctl ||

sys/dev/pci/drm/i915/display/intel_cursor.c

702

plane->cursor.cntl != cntl) {

sys/dev/pci/drm/i915/display/intel_cursor.c

709

plane->cursor.base = base;

sys/dev/pci/drm/i915/display/intel_cursor.c

710

plane->cursor.size = fbc_ctl;

sys/dev/pci/drm/i915/display/intel_cursor.c

711

plane->cursor.cntl = cntl;

sys/dev/pci/drm/i915/display/intel_cursor.c

719

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

722

i9xx_cursor_update_arm(dsb, plane, crtc_state, NULL);

sys/dev/pci/drm/i915/display/intel_cursor.c

725

static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

728

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

739

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/intel_cursor.c

744

val = intel_de_read(display, CURCNTR(display, plane->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

749

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_cursor.c

759

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

76

&plane_state->uapi.plane->dev->mode_config;

sys/dev/pci/drm/i915/display/intel_cursor.c

762

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

770

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_cursor.c

773

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

793

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

796

intel_plane_destroy_state(&plane->base, &plane_state->uapi);

sys/dev/pci/drm/i915/display/intel_cursor.c

809

struct intel_plane *plane = to_intel_plane(_plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

811

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

813

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_cursor.c

858

new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));

sys/dev/pci/drm/i915/display/intel_cursor.c

87

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

894

plane->frontbuffer_bit);

sys/dev/pci/drm/i915/display/intel_cursor.c

897

plane->base.state = &new_plane_state->uapi;

sys/dev/pci/drm/i915/display/intel_cursor.c

932

intel_plane_update_noarm(NULL, plane, crtc_state, new_plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

933

intel_plane_update_arm(NULL, plane, crtc_state, new_plane_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

935

intel_plane_disable_arm(NULL, plane, crtc_state);

sys/dev/pci/drm/i915/display/intel_cursor.c

959

intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);

sys/dev/pci/drm/i915/display/intel_cursor.c

961

intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);

sys/dev/pci/drm/i915/display/intel_cursor.c

965

return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,

sys/dev/pci/drm/i915/display/intel_cursor.c

979

static void intel_cursor_add_size_hints_property(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_cursor.c

981

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_cursor.c

998

drm_plane_add_size_hints_property(&plane->base, hints, num_hints);

sys/dev/pci/drm/i915/display/intel_display.c

1118

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

1121

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1122

if (plane->pipe == crtc->pipe &&

sys/dev/pci/drm/i915/display/intel_display.c

1123

update_planes & BIT(plane->id))

sys/dev/pci/drm/i915/display/intel_display.c

1124

plane->enable_flip_done(plane);

sys/dev/pci/drm/i915/display/intel_display.c

1135

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

1138

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1139

if (plane->pipe == crtc->pipe &&

sys/dev/pci/drm/i915/display/intel_display.c

1140

update_planes & BIT(plane->id))

sys/dev/pci/drm/i915/display/intel_display.c

1141

plane->disable_flip_done(plane);

sys/dev/pci/drm/i915/display/intel_display.c

1155

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

1159

for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1160

if (plane->need_async_flip_toggle_wa &&

sys/dev/pci/drm/i915/display/intel_display.c

1161

plane->pipe == crtc->pipe &&

sys/dev/pci/drm/i915/display/intel_display.c

1162

disable_async_flip_planes & BIT(plane->id)) {

sys/dev/pci/drm/i915/display/intel_display.c

1167

intel_plane_async_flip(NULL, plane,

sys/dev/pci/drm/i915/display/intel_display.c

1300

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

1306

for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

1307

if (crtc->pipe != plane->pipe ||

sys/dev/pci/drm/i915/display/intel_display.c

1308

!(update_mask & BIT(plane->id)))

sys/dev/pci/drm/i915/display/intel_display.c

1311

intel_plane_disable_arm(NULL, plane, new_crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

1314

fb_bits |= plane->frontbuffer_bit;

sys/dev/pci/drm/i915/display/intel_display.c

457

static void assert_plane(struct intel_plane *plane, bool state)

sys/dev/pci/drm/i915/display/intel_display.c

459

struct intel_display *display = to_intel_display(plane->base.dev);

sys/dev/pci/drm/i915/display/intel_display.c

463

cur_state = plane->get_hw_state(plane, &pipe);

sys/dev/pci/drm/i915/display/intel_display.c

467

plane->base.name, str_on_off(state),

sys/dev/pci/drm/i915/display/intel_display.c

477

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

479

for_each_intel_plane_on_crtc(display->drm, crtc, plane)

sys/dev/pci/drm/i915/display/intel_display.c

480

assert_plane_disabled(plane);

sys/dev/pci/drm/i915/display/intel_display.c

5467

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

5471

for_each_new_intel_plane_in_state(state, plane,

sys/dev/pci/drm/i915/display/intel_display.c

5473

assert_plane(plane, plane_state->is_y_plane ||

sys/dev/pci/drm/i915/display/intel_display.c

5940

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

5979

for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,

sys/dev/pci/drm/i915/display/intel_display.c

5981

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_display.c

5991

if (!plane->async_flip) {

sys/dev/pci/drm/i915/display/intel_display.c

5994

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6001

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6014

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

6044

for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,

sys/dev/pci/drm/i915/display/intel_display.c

6046

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_display.c

6055

new_crtc_state->do_async_flip && !plane->async_flip))

sys/dev/pci/drm/i915/display/intel_display.c

6066

if (!plane->async_flip)

sys/dev/pci/drm/i915/display/intel_display.c

6069

if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format,

sys/dev/pci/drm/i915/display/intel_display.c

6073

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_display.c

6090

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6098

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6106

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6114

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6122

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

613

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

6130

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6137

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6145

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6152

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6159

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6167

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_display.c

6180

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

6191

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

627

plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/intel_display.c

629

return plane->max_stride(plane, pixel_format, modifier,

sys/dev/pci/drm/i915/display/intel_display.c

637

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_display.c

642

crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);

sys/dev/pci/drm/i915/display/intel_display.c

644

crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);

sys/dev/pci/drm/i915/display/intel_display.c

650

struct drm_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

660

drm_for_each_plane_mask(plane, display->drm,

sys/dev/pci/drm/i915/display/intel_display.c

662

crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);

sys/dev/pci/drm/i915/display/intel_display.c

663

crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);

sys/dev/pci/drm/i915/display/intel_display.c

668

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_display.c

674

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_display.c

678

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_display.c

685

skl_wm_plane_disable_noatomic(crtc, plane);

sys/dev/pci/drm/i915/display/intel_display.c

7111

struct drm_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

7116

for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

713

intel_plane_disable_arm(NULL, plane, crtc_state);

sys/dev/pci/drm/i915/display/intel_display.c

7167

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

7171

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_display.c

7577

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display.c

7580

for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,

sys/dev/pci/drm/i915/display/intel_display.c

7584

plane->frontbuffer_bit);

sys/dev/pci/drm/i915/display/intel_display.h

289

#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \

sys/dev/pci/drm/i915/display/intel_display.h

292

((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \

sys/dev/pci/drm/i915/display/intel_display.h

295

for_each_if(plane)

sys/dev/pci/drm/i915/display/intel_display.h

305

#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \

sys/dev/pci/drm/i915/display/intel_display.h

308

((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \

sys/dev/pci/drm/i915/display/intel_display.h

311

for_each_if(plane)

sys/dev/pci/drm/i915/display/intel_display.h

329

#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \

sys/dev/pci/drm/i915/display/intel_display.h

332

((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \

sys/dev/pci/drm/i915/display/intel_display.h

336

for_each_if(plane)

sys/dev/pci/drm/i915/display/intel_display.h

357

plane, plane_state, \

sys/dev/pci/drm/i915/display/intel_display.h

359

for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \

sys/dev/pci/drm/i915/display/intel_display.h

362

to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))

sys/dev/pci/drm/i915/display/intel_display.h

501

struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

336

static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

339

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

367

static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

370

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

393

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

395

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

397

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

398

plane_type(plane->base.type));

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

399

intel_plane_uapi_info(m, plane);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

400

intel_plane_hw_info(m, plane);

sys/dev/pci/drm/i915/display/intel_display_driver.c

171

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display_driver.c

173

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_display_driver.c

175

plane->pipe);

sys/dev/pci/drm/i915/display/intel_display_driver.c

177

plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);

sys/dev/pci/drm/i915/display/intel_display_irq.c

84

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_display_irq.c

86

plane = intel_crtc_get_plane(crtc, plane_id);

sys/dev/pci/drm/i915/display/intel_display_irq.c

87

if (!plane || !plane->capture_error)

sys/dev/pci/drm/i915/display/intel_display_irq.c

90

plane->capture_error(crtc, plane, &error);

sys/dev/pci/drm/i915/display/intel_display_irq.c

95

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

19

#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

26

#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1228

#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))

sys/dev/pci/drm/i915/display/intel_display_types.h

1513

unsigned int (*min_alignment)(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_display_types.h

1516

unsigned int (*max_stride)(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_display_types.h

1522

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_display_types.h

1527

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_display_types.h

1532

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_display_types.h

1535

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_display_types.h

1537

bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);

sys/dev/pci/drm/i915/display/intel_display_types.h

1544

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_display_types.h

1548

void (*enable_flip_done)(struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_display_types.h

1549

void (*disable_flip_done)(struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_display_types.h

1551

void (*disable_tiling)(struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_display_types.h

2065

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_display_types.h

2068

drm_atomic_get_plane_state(&state->base, &plane->base);

sys/dev/pci/drm/i915/display/intel_display_types.h

2078

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_display_types.h

2081

&plane->base));

sys/dev/pci/drm/i915/display/intel_display_types.h

2086

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_display_types.h

2089

&plane->base));

sys/dev/pci/drm/i915/display/intel_display_types.h

2198

__drm_device_to_intel_display((p)->uapi.plane->dev)

sys/dev/pci/drm/i915/display/intel_display_types.h

836

u16 plane[I915_MAX_PLANES];

sys/dev/pci/drm/i915/display/intel_fb.c

1140

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1144

unsigned int alignment = plane->min_alignment(plane, fb, color_plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1245

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1250

if (plane->id == PLANE_CURSOR)

sys/dev/pci/drm/i915/display/intel_fb.c

1293

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1296

(plane->fbc && !plane_state->no_fbc_reason &&

sys/dev/pci/drm/i915/display/intel_fb.c

1312

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1332

max_stride = plane->max_stride(plane, fb->base.format->format,

sys/dev/pci/drm/i915/display/intel_fb.c

1493

struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane];

sys/dev/pci/drm/i915/display/intel_fb.c

1521

check_array_bounds(display, view->gtt.rotated.plane, color_plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1546

check_array_bounds(display, view->gtt.remapped.plane, color_plane);

sys/dev/pci/drm/i915/display/intel_fb.c

1664

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fb.c

1667

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_fb.c

1670

if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier))

sys/dev/pci/drm/i915/display/intel_fb.c

1673

plane_min_alignment = plane->min_alignment(plane, fb, 0);

sys/dev/pci/drm/i915/display/intel_fb.c

1678

if (intel_plane_needs_physical(plane))

sys/dev/pci/drm/i915/display/intel_fb.c

1690

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fb.c

1693

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_fb.c

1694

if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier))

sys/dev/pci/drm/i915/display/intel_fb.c

1697

vtd_guard = max_t(unsigned int, vtd_guard, plane->vtd_guard);

sys/dev/pci/drm/i915/display/intel_fb.c

1903

for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)

sys/dev/pci/drm/i915/display/intel_fb.c

1904

size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;

sys/dev/pci/drm/i915/display/intel_fb.c

1914

for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {

sys/dev/pci/drm/i915/display/intel_fb.c

1917

if (rem_info->plane[i].linear)

sys/dev/pci/drm/i915/display/intel_fb.c

1918

plane_size = rem_info->plane[i].size;

sys/dev/pci/drm/i915/display/intel_fb.c

1920

plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;

sys/dev/pci/drm/i915/display/intel_fb.c

2044

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fb.c

2061

max_stride = plane->max_stride(plane, fb->format->format,

sys/dev/pci/drm/i915/display/intel_fb.c

2068

plane->base.base.id, plane->base.name, max_stride);

sys/dev/pci/drm/i915/display/intel_fb.c

620

bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

624

for (i = 0; i < plane->base.modifier_count; i++)

sys/dev/pci/drm/i915/display/intel_fb.c

625

if (plane->base.modifiers[i] == modifier)

sys/dev/pci/drm/i915/display/intel_fb.h

47

bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

244

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

247

if (!intel_plane_needs_physical(plane))

sys/dev/pci/drm/i915/display/intel_fb_pin.c

250

return plane->min_alignment(plane, fb, 0);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

265

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

317

if (intel_plane_needs_physical(plane)) {

sys/dev/pci/drm/i915/display/intel_fb_pin.c

321

plane->surf_offset(plane_state);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

324

plane->surf_offset(plane_state);

sys/dev/pci/drm/i915/display/intel_fbc.c

1017

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1033

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1053

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1088

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1122

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1161

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1194

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1219

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1263

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1265

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1266

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1273

if (fbc->state.plane == plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1297

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1303

intel_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1304

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1308

WARN_ON(fbc_state->plane && fbc_state->plane != plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1310

fbc_state->plane = plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

1332

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

1353

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1354

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1372

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1373

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1402

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

1408

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1409

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1411

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1416

if (fbc->state.plane == plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1425

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1430

intel_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1434

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1585

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1590

intel_atomic_get_old_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1592

intel_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1630

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1633

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1640

if (intel_fbc_can_flip_nuke(state, crtc, plane))

sys/dev/pci/drm/i915/display/intel_fbc.c

1670

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

1673

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1674

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1676

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1681

if (fbc->state.plane == plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1682

need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1693

struct intel_plane *plane = fbc->state.plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

1699

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_fbc.c

1709

fbc->state.plane = NULL;

sys/dev/pci/drm/i915/display/intel_fbc.c

1728

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

1731

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1732

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1734

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1739

if (fbc->state.plane == plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1748

if (fbc->state.plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1749

return fbc->state.plane->frontbuffer_bit;

sys/dev/pci/drm/i915/display/intel_fbc.c

1827

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

1830

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1833

ret = intel_fbc_check_plane(state, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1843

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1847

intel_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1848

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1852

if (fbc->state.plane) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1853

if (fbc->state.plane != plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1857

intel_fbc_update_state(state, crtc, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1887

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_fbc.c

1890

intel_fbc_update_state(state, crtc, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1908

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

1910

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1911

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1913

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1917

if (fbc->state.plane == plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1929

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

1932

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1933

struct intel_fbc *fbc = plane->fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

1935

if (!fbc || plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_fbc.c

1942

if (fbc->state.plane == plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1945

__intel_fbc_enable(state, crtc, plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

1960

if (fbc->underrun_detected || !fbc->state.plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

1968

intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe));

sys/dev/pci/drm/i915/display/intel_fbc.c

203

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

2072

void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_fbc.c

2074

plane->fbc = fbc;

sys/dev/pci/drm/i915/display/intel_fbc.c

2150

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

2166

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_fbc.c

2168

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_fbc.c

2170

if (plane->fbc != fbc)

sys/dev/pci/drm/i915/display/intel_fbc.c

2174

fbc->state.plane == plane ? '*' : ' ',

sys/dev/pci/drm/i915/display/intel_fbc.c

2175

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_fbc.c

2234

struct intel_plane *plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/intel_fbc.c

2236

if (plane->fbc)

sys/dev/pci/drm/i915/display/intel_fbc.c

2237

intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);

sys/dev/pci/drm/i915/display/intel_fbc.c

234

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

242

struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);

sys/dev/pci/drm/i915/display/intel_fbc.c

305

FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

370

enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

408

enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;

sys/dev/pci/drm/i915/display/intel_fbc.c

445

DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

656

dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

659

dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id);

sys/dev/pci/drm/i915/display/intel_fbc.c

725

trace_intel_fbc_activate(fbc->state.plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

735

trace_intel_fbc_deactivate(fbc->state.plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

754

trace_intel_fbc_nuke(fbc->state.plane);

sys/dev/pci/drm/i915/display/intel_fbc.c

87

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_fbc.h

46

void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_fbc.h

54

struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_fbdev.c

407

struct intel_plane *plane =

sys/dev/pci/drm/i915/display/intel_fbdev.c

410

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_fbdev.c

423

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_fbdev.c

430

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_fbdev.c

446

struct intel_plane *plane =

sys/dev/pci/drm/i915/display/intel_fbdev.c

458

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_fbdev.c

470

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_fbdev.c

490

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_fbdev.c

498

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_fbdev.c

516

struct intel_plane *plane =

sys/dev/pci/drm/i915/display/intel_fbdev.c

519

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_fbdev.c

526

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_load_detect.c

26

struct drm_plane *plane;

sys/dev/pci/drm/i915/display/intel_load_detect.c

34

for_each_new_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

378

struct intel_plane *plane =

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

383

if (!plane->get_hw_state(plane, &pipe))

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

391

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

394

intel_plane_disable_noatomic(plane_crtc, plane);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

46

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

474

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

477

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

479

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

482

plane->base.type != DRM_PLANE_TYPE_PRIMARY)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

483

intel_plane_disable_noatomic(crtc, plane);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

54

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

56

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

59

intel_plane_disable_noatomic(crtc, plane);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

659

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

662

for_each_intel_plane(display->drm, plane) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

664

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

669

visible = plane->get_hw_state(plane, &pipe);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

678

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

818

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

838

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

840

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

847

crtc_state->data_rate[plane->id] =

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

853

if (plane_state->uapi.visible && plane->min_cdclk) {

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

855

crtc_state->min_cdclk[plane->id] =

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

858

crtc_state->min_cdclk[plane->id] =

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

863

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

864

crtc_state->min_cdclk[plane->id]);

sys/dev/pci/drm/i915/display/intel_plane.c

100

kfree(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1002

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1023

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_plane.c

1040

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_plane.c

1054

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

110

void intel_plane_destroy(struct drm_plane *plane)

sys/dev/pci/drm/i915/display/intel_plane.c

1113

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_plane.c

112

drm_plane_cleanup(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1121

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_plane.c

113

kfree(to_intel_plane(plane));

sys/dev/pci/drm/i915/display/intel_plane.c

1181

struct intel_plane *plane = to_intel_plane(_plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1182

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1188

intel_atomic_get_old_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1224

ret = drm_gem_plane_helper_prepare_fb(&plane->base, &new_plane_state->uapi);

sys/dev/pci/drm/i915/display/intel_plane.c

126

intel_plane_duplicate_state(struct drm_plane *plane)

sys/dev/pci/drm/i915/display/intel_plane.c

1262

intel_cleanup_plane_fb(struct drm_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

1265

struct intel_display *display = to_intel_display(plane->dev);

sys/dev/pci/drm/i915/display/intel_plane.c

130

intel_state = to_intel_plane_state(plane->state);

sys/dev/pci/drm/i915/display/intel_plane.c

1325

static void intel_panic_flush(struct drm_plane *plane)

sys/dev/pci/drm/i915/display/intel_plane.c

1327

struct intel_plane_state *plane_state = to_intel_plane_state(plane->state);

sys/dev/pci/drm/i915/display/intel_plane.c

1328

struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state);

sys/dev/pci/drm/i915/display/intel_plane.c

1329

struct intel_plane *iplane = to_intel_plane(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

136

__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);

sys/dev/pci/drm/i915/display/intel_plane.c

1384

static int intel_get_scanout_buffer(struct drm_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

1391

struct intel_display *display = to_intel_display(plane->dev);

sys/dev/pci/drm/i915/display/intel_plane.c

1393

if (!plane->state || !plane->state->fb || !plane->state->visible)

sys/dev/pci/drm/i915/display/intel_plane.c

1396

plane_state = to_intel_plane_state(plane->state);

sys/dev/pci/drm/i915/display/intel_plane.c

1444

void intel_plane_helper_add(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_plane.c

1446

if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)

sys/dev/pci/drm/i915/display/intel_plane.c

1447

drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs);

sys/dev/pci/drm/i915/display/intel_plane.c

1449

drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);

sys/dev/pci/drm/i915/display/intel_plane.c

1468

struct intel_plane *uv_plane = to_intel_plane(uv_plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1469

struct intel_plane *y_plane = to_intel_plane(y_plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1504

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1518

crtc_state->enabled_planes &= ~BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

1519

crtc_state->active_planes &= ~BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

1520

crtc_state->update_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

1521

crtc_state->data_rate[plane->id] = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

1522

crtc_state->rel_data_rate[plane->id] = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

1532

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

1542

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_plane.c

1543

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_plane.c

1552

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_plane.c

1556

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/intel_plane.c

1559

if ((crtc_state->nv12_planes & BIT(plane->id)) == 0)

sys/dev/pci/drm/i915/display/intel_plane.c

159

intel_plane_destroy_state(struct drm_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

1595

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

1597

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_plane.c

1600

if ((plane_ids_mask & BIT(plane->id)) == 0)

sys/dev/pci/drm/i915/display/intel_plane.c

1603

plane_state = intel_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1636

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

164

drm_WARN_ON(plane->dev, plane_state->ggtt_vma);

sys/dev/pci/drm/i915/display/intel_plane.c

1640

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_plane.c

1643

if ((joined_pipes & BIT(plane->pipe)) == 0)

sys/dev/pci/drm/i915/display/intel_plane.c

1646

affected_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

165

drm_WARN_ON(plane->dev, plane_state->dpt_vma);

sys/dev/pci/drm/i915/display/intel_plane.c

1711

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

1719

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_plane.c

1720

ret = plane_atomic_check(state, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

1724

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/intel_plane.c

173

bool intel_plane_needs_physical(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_plane.c

175

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

177

return plane->id == PLANE_CURSOR &&

sys/dev/pci/drm/i915/display/intel_plane.c

181

bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,

sys/dev/pci/drm/i915/display/intel_plane.c

188

return plane->can_async_flip && plane->can_async_flip(modifier);

sys/dev/pci/drm/i915/display/intel_plane.c

191

bool intel_plane_format_mod_supported_async(struct drm_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

195

if (!plane->funcs->format_mod_supported(plane, format, modifier))

sys/dev/pci/drm/i915/display/intel_plane.c

198

return intel_plane_can_async_flip(to_intel_plane(plane),

sys/dev/pci/drm/i915/display/intel_plane.c

259

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

264

if (plane->id == PLANE_CURSOR)

sys/dev/pci/drm/i915/display/intel_plane.c

285

skl_plane_relative_data_rate(crtc_state, plane, width, height,

sys/dev/pci/drm/i915/display/intel_plane.c

296

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

299

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

301

intel_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

307

if (!plane_state->uapi.visible || !plane->min_cdclk)

sys/dev/pci/drm/i915/display/intel_plane.c

313

new_crtc_state->min_cdclk[plane->id] =

sys/dev/pci/drm/i915/display/intel_plane.c

314

plane->min_cdclk(new_crtc_state, plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

324

if (new_crtc_state->min_cdclk[plane->id] <=

sys/dev/pci/drm/i915/display/intel_plane.c

325

old_crtc_state->min_cdclk[plane->id])

sys/dev/pci/drm/i915/display/intel_plane.c

340

if (new_crtc_state->min_cdclk[plane->id] <=

sys/dev/pci/drm/i915/display/intel_plane.c

346

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_plane.c

347

new_crtc_state->min_cdclk[plane->id],

sys/dev/pci/drm/i915/display/intel_plane.c

430

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

434

crtc_state->active_planes &= ~BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

435

crtc_state->scaled_planes &= ~BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

436

crtc_state->nv12_planes &= ~BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

437

crtc_state->c8_planes &= ~BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

438

crtc_state->async_flip_planes &= ~BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

439

crtc_state->data_rate[plane->id] = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

440

crtc_state->data_rate_y[plane->id] = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

441

crtc_state->rel_data_rate[plane->id] = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

442

crtc_state->rel_data_rate_y[plane->id] = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

443

crtc_state->min_cdclk[plane->id] = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

458

static bool intel_plane_do_async_flip(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

462

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

464

if (!plane->async_flip)

sys/dev/pci/drm/i915/display/intel_plane.c

490

struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

497

if (plane->id == PLANE_CURSOR)

sys/dev/pci/drm/i915/display/intel_plane.c

519

if (plane->id == PLANE_PRIMARY) {

sys/dev/pci/drm/i915/display/intel_plane.c

531

struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

536

if (plane->id == PLANE_CURSOR)

sys/dev/pci/drm/i915/display/intel_plane.c

589

struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

596

if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) {

sys/dev/pci/drm/i915/display/intel_plane.c

632

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/intel_plane.c

637

new_crtc_state->fb_bits |= plane->frontbuffer_bit;

sys/dev/pci/drm/i915/display/intel_plane.c

647

if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {

sys/dev/pci/drm/i915/display/intel_plane.c

649

new_crtc_state->async_flip_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

650

} else if (plane->need_async_flip_toggle_wa &&

sys/dev/pci/drm/i915/display/intel_plane.c

66

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_plane.c

660

new_crtc_state->async_flip_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

671

struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_plane.c

676

new_crtc_state->enabled_planes &= ~BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

681

ret = plane->check_plane(new_crtc_state, new_plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

686

new_crtc_state->enabled_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

690

new_crtc_state->active_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

694

new_crtc_state->scaled_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

698

new_crtc_state->nv12_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

70

__drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);

sys/dev/pci/drm/i915/display/intel_plane.c

702

new_crtc_state->c8_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

705

new_crtc_state->update_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

709

new_crtc_state->data_rate_y[plane->id] =

sys/dev/pci/drm/i915/display/intel_plane.c

711

new_crtc_state->data_rate[plane->id] =

sys/dev/pci/drm/i915/display/intel_plane.c

714

new_crtc_state->rel_data_rate_y[plane->id] =

sys/dev/pci/drm/i915/display/intel_plane.c

717

new_crtc_state->rel_data_rate[plane->id] =

sys/dev/pci/drm/i915/display/intel_plane.c

721

new_crtc_state->data_rate[plane->id] =

sys/dev/pci/drm/i915/display/intel_plane.c

724

new_crtc_state->rel_data_rate[plane->id] =

sys/dev/pci/drm/i915/display/intel_plane.c

737

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

739

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/intel_plane.c

740

if (plane->id == plane_id)

sys/dev/pci/drm/i915/display/intel_plane.c

741

return plane;

sys/dev/pci/drm/i915/display/intel_plane.c

748

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_plane.c

752

intel_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

754

intel_atomic_get_old_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

757

struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);

sys/dev/pci/drm/i915/display/intel_plane.c

767

intel_crtc_get_plane(primary_crtc, plane->id);

sys/dev/pci/drm/i915/display/intel_plane.c

78

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

80

plane = kzalloc(sizeof(*plane), GFP_KERNEL);

sys/dev/pci/drm/i915/display/intel_plane.c

806

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

81

if (!plane)

sys/dev/pci/drm/i915/display/intel_plane.c

812

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/intel_plane.c

813

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_plane.c

815

if (crtc->pipe != plane->pipe ||

sys/dev/pci/drm/i915/display/intel_plane.c

829

return plane;

sys/dev/pci/drm/i915/display/intel_plane.c

839

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

847

if (plane->fbc)

sys/dev/pci/drm/i915/display/intel_plane.c

848

intel_fbc_dirty_rect_update_noarm(dsb, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

850

if (plane->update_noarm)

sys/dev/pci/drm/i915/display/intel_plane.c

851

plane->update_noarm(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

855

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

86

kfree(plane);

sys/dev/pci/drm/i915/display/intel_plane.c

862

trace_intel_plane_async_flip(plane, crtc, async_flip);

sys/dev/pci/drm/i915/display/intel_plane.c

863

plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);

sys/dev/pci/drm/i915/display/intel_plane.c

867

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

873

if (crtc_state->do_async_flip && plane->async_flip) {

sys/dev/pci/drm/i915/display/intel_plane.c

874

intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);

sys/dev/pci/drm/i915/display/intel_plane.c

879

plane->update_arm(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

883

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.c

888

trace_intel_plane_disable_arm(plane, crtc);

sys/dev/pci/drm/i915/display/intel_plane.c

889

plane->disable_arm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/intel_plane.c

90

intel_plane_state_reset(plane_state, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

900

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

910

for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/i915/display/intel_plane.c

911

if (crtc->pipe != plane->pipe ||

sys/dev/pci/drm/i915/display/intel_plane.c

912

!(update_mask & BIT(plane->id)))

sys/dev/pci/drm/i915/display/intel_plane.c

918

intel_plane_update_noarm(dsb, plane,

sys/dev/pci/drm/i915/display/intel_plane.c

92

plane->base.state = &plane_state->uapi;

sys/dev/pci/drm/i915/display/intel_plane.c

934

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

94

return plane;

sys/dev/pci/drm/i915/display/intel_plane.c

941

while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {

sys/dev/pci/drm/i915/display/intel_plane.c

943

intel_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_plane.c

951

intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

953

intel_plane_disable_arm(dsb, plane, new_crtc_state);

sys/dev/pci/drm/i915/display/intel_plane.c

965

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_plane.c

968

for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/i915/display/intel_plane.c

969

if (crtc->pipe != plane->pipe ||

sys/dev/pci/drm/i915/display/intel_plane.c

97

void intel_plane_free(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/intel_plane.c

970

!(update_mask & BIT(plane->id)))

sys/dev/pci/drm/i915/display/intel_plane.c

978

intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state);

sys/dev/pci/drm/i915/display/intel_plane.c

980

intel_plane_disable_arm(dsb, plane, new_crtc_state);

sys/dev/pci/drm/i915/display/intel_plane.c

99

intel_plane_destroy_state(&plane->base, plane->base.state);

sys/dev/pci/drm/i915/display/intel_plane.h

24

bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,

sys/dev/pci/drm/i915/display/intel_plane.h

41

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.h

46

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.h

50

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.h

54

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.h

57

void intel_plane_free(struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_plane.h

58

void intel_plane_destroy(struct drm_plane *plane);

sys/dev/pci/drm/i915/display/intel_plane.h

59

struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);

sys/dev/pci/drm/i915/display/intel_plane.h

60

void intel_plane_destroy_state(struct drm_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.h

73

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane.h

82

void intel_plane_helper_add(struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_plane.h

83

bool intel_plane_needs_physical(struct intel_plane *plane);

sys/dev/pci/drm/i915/display/intel_plane.h

90

bool intel_plane_format_mod_supported_async(struct drm_plane *plane,

sys/dev/pci/drm/i915/display/intel_plane_initial.c

313

struct intel_plane *plane =

sys/dev/pci/drm/i915/display/intel_plane_initial.c

316

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

33

struct intel_plane *plane =

sys/dev/pci/drm/i915/display/intel_plane_initial.c

348

intel_plane_disable_noatomic(crtc, plane);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

36

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

384

atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits);

sys/dev/pci/drm/i915/display/intel_psr.c

2643

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_psr.c

2649

for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {

sys/dev/pci/drm/i915/display/intel_psr.c

2655

if (plane->id != PLANE_CURSOR)

sys/dev/pci/drm/i915/display/intel_psr.c

2761

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_psr.c

2790

for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,

sys/dev/pci/drm/i915/display/intel_psr.c

2907

for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,

sys/dev/pci/drm/i915/display/intel_psr.c

2926

crtc_state->update_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_psr.c

2939

crtc_state->update_planes |= BIT(plane->id);

sys/dev/pci/drm/i915/display/intel_sprite.c

1083

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1085

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1113

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1115

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1138

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

1142

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1143

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1168

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

1172

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1173

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1209

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

1212

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1213

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1222

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

1225

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1233

g4x_sprite_get_hw_state(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

1236

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1241

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/intel_sprite.c

1246

ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

1248

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

143

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

145

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

146

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_sprite.c

1596

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/intel_sprite.c

1604

plane = intel_plane_alloc();

sys/dev/pci/drm/i915/display/intel_sprite.c

1605

if (IS_ERR(plane))

sys/dev/pci/drm/i915/display/intel_sprite.c

1606

return plane;

sys/dev/pci/drm/i915/display/intel_sprite.c

1609

plane->update_noarm = vlv_sprite_update_noarm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1610

plane->update_arm = vlv_sprite_update_arm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1611

plane->disable_arm = vlv_sprite_disable_arm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1612

plane->capture_error = vlv_sprite_capture_error;

sys/dev/pci/drm/i915/display/intel_sprite.c

1613

plane->get_hw_state = vlv_sprite_get_hw_state;

sys/dev/pci/drm/i915/display/intel_sprite.c

1614

plane->check_plane = vlv_sprite_check;

sys/dev/pci/drm/i915/display/intel_sprite.c

1615

plane->surf_offset = i965_plane_surf_offset;

sys/dev/pci/drm/i915/display/intel_sprite.c

1616

plane->max_stride = i965_plane_max_stride;

sys/dev/pci/drm/i915/display/intel_sprite.c

1617

plane->min_alignment = vlv_plane_min_alignment;

sys/dev/pci/drm/i915/display/intel_sprite.c

1618

plane->min_cdclk = vlv_plane_min_cdclk;

sys/dev/pci/drm/i915/display/intel_sprite.c

1622

plane->vtd_guard = 128;

sys/dev/pci/drm/i915/display/intel_sprite.c

1634

plane->update_noarm = ivb_sprite_update_noarm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1635

plane->update_arm = ivb_sprite_update_arm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1636

plane->disable_arm = ivb_sprite_disable_arm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1637

plane->capture_error = ivb_sprite_capture_error;

sys/dev/pci/drm/i915/display/intel_sprite.c

1638

plane->get_hw_state = ivb_sprite_get_hw_state;

sys/dev/pci/drm/i915/display/intel_sprite.c

1639

plane->check_plane = g4x_sprite_check;

sys/dev/pci/drm/i915/display/intel_sprite.c

1640

plane->surf_offset = i965_plane_surf_offset;

sys/dev/pci/drm/i915/display/intel_sprite.c

1643

plane->max_stride = hsw_sprite_max_stride;

sys/dev/pci/drm/i915/display/intel_sprite.c

1644

plane->min_cdclk = hsw_plane_min_cdclk;

sys/dev/pci/drm/i915/display/intel_sprite.c

1646

plane->max_stride = g4x_sprite_max_stride;

sys/dev/pci/drm/i915/display/intel_sprite.c

1647

plane->min_cdclk = ivb_sprite_min_cdclk;

sys/dev/pci/drm/i915/display/intel_sprite.c

1650

plane->min_alignment = g4x_sprite_min_alignment;

sys/dev/pci/drm/i915/display/intel_sprite.c

1653

plane->vtd_guard = 64;

sys/dev/pci/drm/i915/display/intel_sprite.c

1660

plane->update_noarm = g4x_sprite_update_noarm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1661

plane->update_arm = g4x_sprite_update_arm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1662

plane->disable_arm = g4x_sprite_disable_arm;

sys/dev/pci/drm/i915/display/intel_sprite.c

1663

plane->capture_error = g4x_sprite_capture_error;

sys/dev/pci/drm/i915/display/intel_sprite.c

1664

plane->get_hw_state = g4x_sprite_get_hw_state;

sys/dev/pci/drm/i915/display/intel_sprite.c

1665

plane->check_plane = g4x_sprite_check;

sys/dev/pci/drm/i915/display/intel_sprite.c

1666

plane->surf_offset = i965_plane_surf_offset;

sys/dev/pci/drm/i915/display/intel_sprite.c

1667

plane->max_stride = g4x_sprite_max_stride;

sys/dev/pci/drm/i915/display/intel_sprite.c

1668

plane->min_alignment = g4x_sprite_min_alignment;

sys/dev/pci/drm/i915/display/intel_sprite.c

1669

plane->min_cdclk = g4x_sprite_min_cdclk;

sys/dev/pci/drm/i915/display/intel_sprite.c

1672

plane->vtd_guard = 64;

sys/dev/pci/drm/i915/display/intel_sprite.c

1696

plane->pipe = pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

1697

plane->id = PLANE_SPRITE0 + sprite;

sys/dev/pci/drm/i915/display/intel_sprite.c

1698

plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);

sys/dev/pci/drm/i915/display/intel_sprite.c

1702

ret = drm_universal_plane_init(display->drm, &plane->base,

sys/dev/pci/drm/i915/display/intel_sprite.c

1712

drm_plane_create_rotation_property(&plane->base,

sys/dev/pci/drm/i915/display/intel_sprite.c

1716

drm_plane_create_color_properties(&plane->base,

sys/dev/pci/drm/i915/display/intel_sprite.c

1725

drm_plane_create_zpos_immutable_property(&plane->base, zpos);

sys/dev/pci/drm/i915/display/intel_sprite.c

1727

intel_plane_helper_add(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

1729

return plane;

sys/dev/pci/drm/i915/display/intel_sprite.c

1732

intel_plane_free(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

345

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

347

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

348

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_sprite.c

367

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

371

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

372

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

373

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_sprite.c

389

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

393

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

394

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

395

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_sprite.c

436

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

439

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

440

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

441

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_sprite.c

448

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

451

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

453

error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

454

error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

455

error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

459

vlv_sprite_get_hw_state(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

462

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

464

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_sprite.c

468

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/intel_sprite.c

473

ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

475

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

71

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

73

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/intel_sprite.c

762

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

763

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

790

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

794

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

795

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

821

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

825

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

826

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

866

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

869

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

870

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

880

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

883

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

891

ivb_sprite_get_hw_state(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

894

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.c

899

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/intel_sprite.c

904

ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

906

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/intel_sprite.c

960

g4x_sprite_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

975

hsw_sprite_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

986

static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/intel_sprite.c

990

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/intel_sprite.h

18

enum pipe pipe, int plane);

sys/dev/pci/drm/i915/display/intel_sprite.h

30

int pipe, int plane)

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

104

to_intel_plane(plane)->pipe);

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

20

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

29

if (plane->id == PLANE_PRIMARY &&

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

37

if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_PRIMARY &&

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

47

struct drm_plane *plane;

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

67

plane = drm_plane_find(dev, file_priv, set->plane_id);

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

68

if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

77

to_intel_plane(plane)->id >= PLANE_3 &&

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

83

state = drm_atomic_state_alloc(plane->dev);

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

92

plane_state = drm_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/i915/display/intel_wm.c

122

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/intel_wm.c

136

if (plane->id == PLANE_CURSOR)

sys/dev/pci/drm/i915/display/intel_wm_types.h

27

u16 plane[I915_MAX_PLANES];

sys/dev/pci/drm/i915/display/intel_wm_types.h

32

u16 plane;

sys/dev/pci/drm/i915/display/intel_wm_types.h

38

u8 plane[I915_MAX_PLANES];

sys/dev/pci/drm/i915/display/skl_scaler.c

301

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_scaler.c

307

if (!icl_is_hdr_plane(display, plane->id) &&

sys/dev/pci/drm/i915/display/skl_scaler.c

312

drm_plane_index(&plane->base),

sys/dev/pci/drm/i915/display/skl_scaler.c

401

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_scaler.c

405

} else if (icl_is_hdr_plane(display, plane->id)) {

sys/dev/pci/drm/i915/display/skl_scaler.c

531

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/skl_scaler.c

541

if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe))

sys/dev/pci/drm/i915/display/skl_scaler.c

544

plane_state = intel_atomic_get_new_plane_state(state, plane);

sys/dev/pci/drm/i915/display/skl_scaler.c

554

plane_state = intel_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/i915/display/skl_scaler.c

560

crtc, "PLANE", plane->base.base.id,

sys/dev/pci/drm/i915/display/skl_scaler.c

627

struct intel_plane *plane =

sys/dev/pci/drm/i915/display/skl_scaler.c

630

ret = setup_plane_scaler(state, crtc, plane);

sys/dev/pci/drm/i915/display/skl_scaler.c

803

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_scaler.c

807

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_scaler.c

809

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_scaler.c

831

!icl_is_hdr_plane(display, plane->id)) {

sys/dev/pci/drm/i915/display/skl_scaler.c

847

ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |

sys/dev/pci/drm/i915/display/skl_scaler.c

850

trace_intel_plane_scaler_update_arm(plane, scaler_id,

sys/dev/pci/drm/i915/display/skl_scaler.h

30

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1233

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1239

if (fb->format->is_yuv && !icl_is_hdr_plane(display, plane->id)) {

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1352

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1355

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1356

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1357

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1379

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1383

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1384

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1385

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1405

skl_write_plane_wm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1410

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1414

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1415

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1416

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1425

if (plane->need_async_flip_toggle_wa &&

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1426

crtc_state->async_flip_planes & BIT(plane->id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1462

skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1476

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1481

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1482

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1498

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1513

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1518

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1523

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1527

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1528

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1529

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1587

icl_program_input_csc(dsb, plane, plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1589

skl_write_plane_wm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1596

icl_plane_csc_load_black(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1598

icl_plane_update_sel_fetch_noarm(dsb, plane, crtc_state, plane_state, color_plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1602

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1606

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1607

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1613

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1616

icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1621

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1625

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1626

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1627

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1641

skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1643

icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1657

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1660

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1662

error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1663

error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1664

error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1669

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1674

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1675

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1676

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1711

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1722

plane->base.base.id, plane->base.name, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1730

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1742

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1750

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1775

plane->base.base.id, plane->base.name, &fb->format->format);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1789

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1799

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1810

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1828

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1841

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1853

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1876

static int intel_plane_min_width(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1881

if (plane->min_width)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1882

return plane->min_width(fb, color_plane, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1887

static int intel_plane_max_width(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1892

if (plane->max_width)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1893

return plane->max_width(fb, color_plane, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1898

static int intel_plane_max_height(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1903

if (plane->max_height)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1904

return plane->max_height(fb, color_plane, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1914

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1919

unsigned int alignment = plane->min_alignment(plane, fb, ccs_plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1959

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1963

unsigned int alignment = plane->min_alignment(plane, fb, 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1994

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2010

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2017

int min_width = intel_plane_min_width(plane, fb, 0, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2018

int max_width = intel_plane_max_width(plane, fb, 0, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2019

int max_height = intel_plane_max_height(plane, fb, 0, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2020

unsigned int alignment = plane->min_alignment(plane, fb, 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2028

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2056

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2083

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2089

int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2090

int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2101

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2112

unsigned int alignment = plane->min_alignment(plane, fb, uv_plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2136

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2306

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2364

icl_is_hdr_plane(display, plane->id))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2379

struct intel_plane *uv_plane = to_intel_plane(uv_plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2380

struct intel_plane *y_plane = to_intel_plane(y_plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2496

struct intel_plane *plane = to_intel_plane(_plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2498

if (!intel_fb_plane_supports_modifier(plane, modifier))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2550

struct intel_plane *plane = to_intel_plane(_plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2552

if (!intel_fb_plane_supports_modifier(plane, modifier))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2604

struct intel_plane *plane = to_intel_plane(_plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2606

if (!intel_fb_plane_supports_modifier(plane, modifier))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2684

skl_plane_enable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2686

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2687

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2690

bdw_enable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2695

skl_plane_disable_flip_done(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2697

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2698

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2701

bdw_disable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2785

static void skl_disable_tiling(struct intel_plane *plane)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2787

struct intel_plane_state *state = to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2788

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2792

plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2802

intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2805

intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2807

intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id),

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2816

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2826

plane = intel_plane_alloc();

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2827

if (IS_ERR(plane))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2828

return plane;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2830

plane->pipe = pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2831

plane->id = plane_id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2832

plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2834

intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2837

plane->max_width = xe3_plane_max_width;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2838

plane->max_height = icl_plane_max_height;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2839

plane->min_cdclk = icl_plane_min_cdclk;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2841

plane->min_width = icl_plane_min_width;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2843

plane->max_width = icl_hdr_plane_max_width;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2845

plane->max_width = icl_sdr_plane_max_width;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2846

plane->max_height = icl_plane_max_height;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2847

plane->min_cdclk = icl_plane_min_cdclk;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2849

plane->max_width = glk_plane_max_width;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2850

plane->max_height = skl_plane_max_height;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2851

plane->min_cdclk = glk_plane_min_cdclk;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2853

plane->max_width = skl_plane_max_width;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2854

plane->max_height = skl_plane_max_height;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2855

plane->min_cdclk = skl_plane_min_cdclk;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2857

plane->disable_tiling = skl_disable_tiling;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2859

plane->surf_offset = skl_plane_surf_offset;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2862

plane->max_stride = adl_plane_max_stride;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2864

plane->max_stride = skl_plane_max_stride;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2867

plane->min_alignment = tgl_plane_min_alignment;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2869

plane->min_alignment = skl_plane_min_alignment;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2872

plane->vtd_guard = DISPLAY_VER(display) >= 10 ? 168 : 136;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2875

plane->update_noarm = icl_plane_update_noarm;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2876

plane->update_arm = icl_plane_update_arm;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2877

plane->disable_arm = icl_plane_disable_arm;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2879

plane->update_noarm = skl_plane_update_noarm;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2880

plane->update_arm = skl_plane_update_arm;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2881

plane->disable_arm = skl_plane_disable_arm;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2883

plane->capture_error = skl_plane_capture_error;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2884

plane->get_hw_state = skl_plane_get_hw_state;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2885

plane->check_plane = skl_plane_check;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2888

plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(display, 9, 10);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2889

plane->async_flip = skl_plane_async_flip;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2890

plane->enable_flip_done = skl_plane_enable_flip_done;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2891

plane->disable_flip_done = skl_plane_disable_flip_done;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2894

plane->can_async_flip = tgl_plane_can_async_flip;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2896

plane->can_async_flip = icl_plane_can_async_flip;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2898

plane->can_async_flip = skl_plane_can_async_flip;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2940

ret = drm_universal_plane_init(display->drm, &plane->base,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2962

drm_plane_create_rotation_property(&plane->base,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2971

drm_plane_create_color_properties(&plane->base,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2978

drm_plane_create_alpha_property(&plane->base);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2979

drm_plane_create_blend_mode_property(&plane->base,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2984

drm_plane_create_zpos_immutable_property(&plane->base, plane_id);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2987

drm_plane_enable_fb_damage_clips(&plane->base);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2990

drm_plane_create_scaling_filter_property(&plane->base,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2994

intel_plane_helper_add(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2996

return plane;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2999

intel_plane_free(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3010

struct intel_plane *plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3011

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3020

if (!plane->get_hw_state(plane, &pipe))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3167

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3182

struct intel_plane *plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3184

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3185

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

474

plane_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

490

adl_plane_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

497

return plane_max_stride(plane, pixel_format,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

503

skl_plane_max_stride(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

510

return plane_max_stride(plane, pixel_format,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

588

static u32 tgl_plane_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

592

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

606

intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))

sys/dev/pci/drm/i915/display/skl_universal_plane.c

637

static u32 skl_plane_min_alignment(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

684

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

687

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

688

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

689

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

829

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

832

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

833

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

834

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

875

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

878

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

879

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

880

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

882

skl_write_plane_wm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

889

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

892

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

893

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

898

intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

903

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

906

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

907

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

908

enum pipe pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

913

skl_write_plane_wm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

915

icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

921

skl_plane_get_hw_state(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

924

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

926

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

930

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

935

ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

937

*pipe = plane->pipe;

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

106

#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

11

#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

116

#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

12

_PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

128

#define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

13

#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

14

(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

140

#define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

148

#define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

15

#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

157

#define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

16

_MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

168

#define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

17

#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

178

#define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

18

_MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

190

#define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

198

#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

20

#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

206

#define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

21

_PICK_EVEN_2RANGES((plane), PLANE_5, \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

217

#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

225

#define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

249

#define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

26

#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

27

_MMIO(_SEL_FETCH((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

273

#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

281

#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

289

#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

297

#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

305

#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

313

#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

320

#define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

333

#define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

341

#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

349

#define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

35

#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

357

#define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

366

#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

374

#define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

388

#define PLANE_MIN_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

406

#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

422

#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

437

#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h

452

#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\

sys/dev/pci/drm/i915/display/skl_watermark.c

1258

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/skl_watermark.c

1260

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

1265

plane->async_flip;

sys/dev/pci/drm/i915/display/skl_watermark.c

1270

struct intel_plane *plane, int width, int height,

sys/dev/pci/drm/i915/display/skl_watermark.c

1278

if (use_minimal_wm0_only(crtc_state, plane))

sys/dev/pci/drm/i915/display/skl_watermark.c

1791

static bool xe3_auto_min_alloc_capable(struct intel_plane *plane, int level)

sys/dev/pci/drm/i915/display/skl_watermark.c

1793

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

1795

return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR;

sys/dev/pci/drm/i915/display/skl_watermark.c

1799

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_watermark.c

1812

(use_minimal_wm0_only(crtc_state, plane) && level > 0)) {

sys/dev/pci/drm/i915/display/skl_watermark.c

1930

result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level);

sys/dev/pci/drm/i915/display/skl_watermark.c

1938

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_watermark.c

1950

skl_compute_plane_wm(crtc_state, plane, level, latency,

sys/dev/pci/drm/i915/display/skl_watermark.c

1958

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_watermark.c

1971

skl_compute_plane_wm(crtc_state, plane, 0, latency,

sys/dev/pci/drm/i915/display/skl_watermark.c

2041

struct intel_plane *plane, int color_plane)

sys/dev/pci/drm/i915/display/skl_watermark.c

2044

struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];

sys/dev/pci/drm/i915/display/skl_watermark.c

2053

skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);

sys/dev/pci/drm/i915/display/skl_watermark.c

2059

tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);

sys/dev/pci/drm/i915/display/skl_watermark.c

2070

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/skl_watermark.c

2072

struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];

sys/dev/pci/drm/i915/display/skl_watermark.c

2084

skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);

sys/dev/pci/drm/i915/display/skl_watermark.c

2092

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

2093

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_watermark.c

2104

plane, 0);

sys/dev/pci/drm/i915/display/skl_watermark.c

2110

plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

2122

struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

2123

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_watermark.c

2147

plane, 1);

sys/dev/pci/drm/i915/display/skl_watermark.c

2152

plane, 0);

sys/dev/pci/drm/i915/display/skl_watermark.c

2367

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/skl_watermark.c

2370

for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2376

if (plane->pipe != crtc->pipe)

sys/dev/pci/drm/i915/display/skl_watermark.c

2465

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/skl_watermark.c

2467

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2469

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_watermark.c

2479

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_watermark.c

2483

plane_state = intel_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

2626

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_watermark.c

2633

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

2652

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

2679

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

2698

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

2721

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/skl_watermark.c

2735

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2736

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_watermark.c

2746

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

2751

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2752

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_watermark.c

2761

skl_print_plane_changes(display, plane, old_wm, new_wm);

sys/dev/pci/drm/i915/display/skl_watermark.c

2766

static bool skl_plane_selected_wm_equals(struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_watermark.c

2770

struct intel_display *display = to_intel_display(plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

2779

if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level),

sys/dev/pci/drm/i915/display/skl_watermark.c

2780

skl_plane_wm_level(new_pipe_wm, plane->id, level)))

sys/dev/pci/drm/i915/display/skl_watermark.c

2785

const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];

sys/dev/pci/drm/i915/display/skl_watermark.c

2786

const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];

sys/dev/pci/drm/i915/display/skl_watermark.c

2793

return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id),

sys/dev/pci/drm/i915/display/skl_watermark.c

2794

skl_plane_trans_wm(new_pipe_wm, plane->id));

sys/dev/pci/drm/i915/display/skl_watermark.c

2827

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/skl_watermark.c

2829

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

2831

enum plane_id plane_id = plane->id;

sys/dev/pci/drm/i915/display/skl_watermark.c

2842

skl_plane_selected_wm_equals(plane,

sys/dev/pci/drm/i915/display/skl_watermark.c

2849

plane->base.base.id, plane->base.name);

sys/dev/pci/drm/i915/display/skl_watermark.c

2853

plane_state = intel_atomic_get_plane_state(state, plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

3764

struct intel_plane *plane = to_intel_plane(crtc->base.primary);

sys/dev/pci/drm/i915/display/skl_watermark.c

3766

to_intel_plane_state(plane->base.state);

sys/dev/pci/drm/i915/display/skl_watermark.c

3771

intel_plane_disable_noatomic(crtc, plane);

sys/dev/pci/drm/i915/display/skl_watermark.c

3808

struct intel_plane *plane)

sys/dev/pci/drm/i915/display/skl_watermark.c

3817

skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0);

sys/dev/pci/drm/i915/display/skl_watermark.c

3818

skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[plane->id], 0, 0);

sys/dev/pci/drm/i915/display/skl_watermark.c

3820

crtc_state->wm.skl.plane_min_ddb[plane->id] = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

3821

crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

3823

memset(&crtc_state->wm.skl.raw.planes[plane->id], 0,

sys/dev/pci/drm/i915/display/skl_watermark.c

3824

sizeof(crtc_state->wm.skl.raw.planes[plane->id]));

sys/dev/pci/drm/i915/display/skl_watermark.c

3825

memset(&crtc_state->wm.skl.optimal.planes[plane->id], 0,

sys/dev/pci/drm/i915/display/skl_watermark.c

3826

sizeof(crtc_state->wm.skl.optimal.planes[plane->id]));

sys/dev/pci/drm/i915/display/skl_watermark.c

3843

struct intel_plane *plane;

sys/dev/pci/drm/i915/display/skl_watermark.c

3867

for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

sys/dev/pci/drm/i915/display/skl_watermark.c

3873

hw_wm_level = &hw->wm.planes[plane->id].wm[level];

sys/dev/pci/drm/i915/display/skl_watermark.c

3874

sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);

sys/dev/pci/drm/i915/display/skl_watermark.c

3881

plane->base.base.id, plane->base.name, level,

sys/dev/pci/drm/i915/display/skl_watermark.c

3890

hw_wm_level = &hw->wm.planes[plane->id].trans_wm;

sys/dev/pci/drm/i915/display/skl_watermark.c

3891

sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);

sys/dev/pci/drm/i915/display/skl_watermark.c

3896

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

3905

hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;

sys/dev/pci/drm/i915/display/skl_watermark.c

3906

sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;

sys/dev/pci/drm/i915/display/skl_watermark.c

3912

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

3921

hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;

sys/dev/pci/drm/i915/display/skl_watermark.c

3922

sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;

sys/dev/pci/drm/i915/display/skl_watermark.c

3928

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

3938

hw_ddb_entry = &hw->ddb[plane->id];

sys/dev/pci/drm/i915/display/skl_watermark.c

3939

sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[plane->id];

sys/dev/pci/drm/i915/display/skl_watermark.c

3944

plane->base.base.id, plane->base.name,

sys/dev/pci/drm/i915/display/skl_watermark.c

600

struct intel_plane *plane,

sys/dev/pci/drm/i915/display/skl_watermark.c

634

struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor);

sys/dev/pci/drm/i915/display/skl_watermark.c

650

skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);

sys/dev/pci/drm/i915/display/skl_watermark.h

42

struct intel_plane *plane);

sys/dev/pci/drm/i915/display/skl_watermark.h

59

struct intel_plane *plane, int width,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1270

int plane;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1283

int plane;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1312

info->plane = gen8_plane_code[v].plane;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1319

if (info->plane == PLANE_A) {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1323

} else if (info->plane == PLANE_B) {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1343

u32 plane = (dword0 & GENMASK(12, 8)) >> 8;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1345

info->plane = PRIMARY_PLANE;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1347

switch (plane) {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1364

info->plane = SPRITE_PLANE;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1369

info->plane = SPRITE_PLANE;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1374

info->plane = SPRITE_PLANE;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1378

gvt_vgpu_err("unknown plane code %d\n", plane);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1443

if (info->plane == PLANE_PRIMARY)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

213

struct intel_vgpu_primary_plane_format *plane)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

225

plane->enabled = !!(val & DISP_ENABLE);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

226

if (!plane->enabled)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

230

plane->tiled = val & PLANE_CTL_TILED_MASK;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

242

plane->bpp = skl_pixel_formats[fmt].bpp;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

243

plane->drm_format = skl_pixel_formats[fmt].drm_format;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

245

plane->tiled = val & DISP_TILED;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

247

plane->bpp = bdw_pixel_formats[fmt].bpp;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

248

plane->drm_format = bdw_pixel_formats[fmt].drm_format;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

251

if (!plane->bpp) {

sys/dev/pci/drm/i915/gvt/fb_decoder.c

256

plane->hw_format = fmt;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

258

plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

259

if (!vgpu_gmadr_is_valid(vgpu, plane->base))

sys/dev/pci/drm/i915/gvt/fb_decoder.c

262

plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

263

if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {

sys/dev/pci/drm/i915/gvt/fb_decoder.c

265

plane->base);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

269

plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,

sys/dev/pci/drm/i915/gvt/fb_decoder.c

272

_PRI_PLANE_STRIDE_MASK, plane->bpp);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

274

plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>

sys/dev/pci/drm/i915/gvt/fb_decoder.c

276

plane->width += 1;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

277

plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &

sys/dev/pci/drm/i915/gvt/fb_decoder.c

279

plane->height += 1; /* raw height is one minus the real value */

sys/dev/pci/drm/i915/gvt/fb_decoder.c

282

plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>

sys/dev/pci/drm/i915/gvt/fb_decoder.c

284

plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>

sys/dev/pci/drm/i915/gvt/fb_decoder.c

344

struct intel_vgpu_cursor_plane_format *plane)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

358

plane->enabled = (mode != MCURSOR_MODE_DISABLE);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

359

if (!plane->enabled)

sys/dev/pci/drm/i915/gvt/fb_decoder.c

368

plane->mode = mode;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

369

plane->bpp = cursor_pixel_formats[index].bpp;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

370

plane->drm_format = cursor_pixel_formats[index].drm_format;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

371

plane->width = cursor_pixel_formats[index].width;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

372

plane->height = cursor_pixel_formats[index].height;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

382

plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

383

if (!vgpu_gmadr_is_valid(vgpu, plane->base))

sys/dev/pci/drm/i915/gvt/fb_decoder.c

386

plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

387

if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {

sys/dev/pci/drm/i915/gvt/fb_decoder.c

389

plane->base);

sys/dev/pci/drm/i915/gvt/fb_decoder.c

394

plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

395

plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

396

plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

397

plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

399

plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));

sys/dev/pci/drm/i915/gvt/fb_decoder.c

400

plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));

sys/dev/pci/drm/i915/gvt/fb_decoder.h

156

struct intel_vgpu_primary_plane_format *plane);

sys/dev/pci/drm/i915/gvt/fb_decoder.h

158

struct intel_vgpu_cursor_plane_format *plane);

sys/dev/pci/drm/i915/gvt/handlers.c

1072

enum plane_id plane = REG_50080_TO_PLANE(offset);

sys/dev/pci/drm/i915/gvt/handlers.c

1073

int event = SKL_FLIP_EVENT(pipe, plane);

sys/dev/pci/drm/i915/gvt/handlers.c

1076

if (plane == PLANE_PRIMARY) {

sys/dev/pci/drm/i915/gvt/reg.h

60

#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))

sys/dev/pci/drm/i915/i915_debugfs.c

223

vma->gtt_view.rotated.plane[0].width,

sys/dev/pci/drm/i915/i915_debugfs.c

224

vma->gtt_view.rotated.plane[0].height,

sys/dev/pci/drm/i915/i915_debugfs.c

225

vma->gtt_view.rotated.plane[0].src_stride,

sys/dev/pci/drm/i915/i915_debugfs.c

226

vma->gtt_view.rotated.plane[0].dst_stride,

sys/dev/pci/drm/i915/i915_debugfs.c

227

vma->gtt_view.rotated.plane[0].offset,

sys/dev/pci/drm/i915/i915_debugfs.c

228

vma->gtt_view.rotated.plane[1].width,

sys/dev/pci/drm/i915/i915_debugfs.c

229

vma->gtt_view.rotated.plane[1].height,

sys/dev/pci/drm/i915/i915_debugfs.c

230

vma->gtt_view.rotated.plane[1].src_stride,

sys/dev/pci/drm/i915/i915_debugfs.c

231

vma->gtt_view.rotated.plane[1].dst_stride,

sys/dev/pci/drm/i915/i915_debugfs.c

232

vma->gtt_view.rotated.plane[1].offset);

sys/dev/pci/drm/i915/i915_debugfs.c

237

vma->gtt_view.remapped.plane[0].width,

sys/dev/pci/drm/i915/i915_debugfs.c

238

vma->gtt_view.remapped.plane[0].height,

sys/dev/pci/drm/i915/i915_debugfs.c

239

vma->gtt_view.remapped.plane[0].src_stride,

sys/dev/pci/drm/i915/i915_debugfs.c

240

vma->gtt_view.remapped.plane[0].dst_stride,

sys/dev/pci/drm/i915/i915_debugfs.c

241

vma->gtt_view.remapped.plane[0].offset,

sys/dev/pci/drm/i915/i915_debugfs.c

242

vma->gtt_view.remapped.plane[1].width,

sys/dev/pci/drm/i915/i915_debugfs.c

243

vma->gtt_view.remapped.plane[1].height,

sys/dev/pci/drm/i915/i915_debugfs.c

244

vma->gtt_view.remapped.plane[1].src_stride,

sys/dev/pci/drm/i915/i915_debugfs.c

245

vma->gtt_view.remapped.plane[1].dst_stride,

sys/dev/pci/drm/i915/i915_debugfs.c

246

vma->gtt_view.remapped.plane[1].offset);

sys/dev/pci/drm/i915/i915_gtt_view_types.h

28

struct intel_remapped_plane_info plane[2];

sys/dev/pci/drm/i915/i915_gtt_view_types.h

37

struct intel_remapped_plane_info plane[4];

sys/dev/pci/drm/i915/i915_reg.h

813

#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))

sys/dev/pci/drm/i915/i915_vma.c

1049

for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)

sys/dev/pci/drm/i915/i915_vma.c

1050

sg = rotate_pages(obj, rot_info->plane[i].offset,

sys/dev/pci/drm/i915/i915_vma.c

1051

rot_info->plane[i].width, rot_info->plane[i].height,

sys/dev/pci/drm/i915/i915_vma.c

1052

rot_info->plane[i].src_stride,

sys/dev/pci/drm/i915/i915_vma.c

1053

rot_info->plane[i].dst_stride,

sys/dev/pci/drm/i915/i915_vma.c

1063

obj->base.size, rot_info->plane[0].width,

sys/dev/pci/drm/i915/i915_vma.c

1064

rot_info->plane[0].height, size);

sys/dev/pci/drm/i915/i915_vma.c

1213

if (rem_info->plane[color_plane].linear)

sys/dev/pci/drm/i915/i915_vma.c

1215

rem_info->plane[color_plane].offset,

sys/dev/pci/drm/i915/i915_vma.c

1217

rem_info->plane[color_plane].size,

sys/dev/pci/drm/i915/i915_vma.c

1223

rem_info->plane[color_plane].offset,

sys/dev/pci/drm/i915/i915_vma.c

1225

rem_info->plane[color_plane].width,

sys/dev/pci/drm/i915/i915_vma.c

1226

rem_info->plane[color_plane].height,

sys/dev/pci/drm/i915/i915_vma.c

1227

rem_info->plane[color_plane].src_stride,

sys/dev/pci/drm/i915/i915_vma.c

1228

rem_info->plane[color_plane].dst_stride,

sys/dev/pci/drm/i915/i915_vma.c

1259

for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)

sys/dev/pci/drm/i915/i915_vma.c

1271

obj->base.size, rem_info->plane[0].width,

sys/dev/pci/drm/i915/i915_vma.c

1272

rem_info->plane[0].height, size);

sys/dev/pci/drm/i915/i915_vma_types.h

107

BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=

sys/dev/pci/drm/i915/i915_vma_types.h

108

offsetof(struct intel_rotation_info, plane[0]));

sys/dev/pci/drm/i915/i915_vma_types.h

110

BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=

sys/dev/pci/drm/i915/i915_vma_types.h

111

offsetofend(struct intel_rotation_info, plane[1]));

sys/dev/pci/drm/i915/selftests/i915_vma.c

1006

.rotated.plane[0] = *p,

sys/dev/pci/drm/i915/selftests/i915_vma.c

1008

struct intel_remapped_plane_info *plane_info = view.rotated.plane;

sys/dev/pci/drm/i915/selftests/i915_vma.c

368

return (r->plane[n].src_stride * (r->plane[n].height - y - 1) +

sys/dev/pci/drm/i915/selftests/i915_vma.c

369

r->plane[n].offset + x);

sys/dev/pci/drm/i915/selftests/i915_vma.c

379

for (x = 0; x < r->plane[n].width; x++) {

sys/dev/pci/drm/i915/selftests/i915_vma.c

382

for (y = 0; y < r->plane[n].height; y++) {

sys/dev/pci/drm/i915/selftests/i915_vma.c

411

left = (r->plane[n].dst_stride - y) * PAGE_SIZE;

sys/dev/pci/drm/i915/selftests/i915_vma.c

445

return (r->plane[n].src_stride * y +

sys/dev/pci/drm/i915/selftests/i915_vma.c

446

r->plane[n].offset + x);

sys/dev/pci/drm/i915/selftests/i915_vma.c

458

for (y = 0; y < r->plane[n].height; y++) {

sys/dev/pci/drm/i915/selftests/i915_vma.c

459

for (x = 0; x < r->plane[n].width; x++) {

sys/dev/pci/drm/i915/selftests/i915_vma.c

504

left = (r->plane[n].dst_stride - r->plane[n].width) * PAGE_SIZE;

sys/dev/pci/drm/i915/selftests/i915_vma.c

597

.remapped.plane[0] = *a,

sys/dev/pci/drm/i915/selftests/i915_vma.c

598

.remapped.plane[1] = *b,

sys/dev/pci/drm/i915/selftests/i915_vma.c

600

struct intel_remapped_plane_info *plane_info = view.remapped.plane;

sys/dev/pci/drm/i915/selftests/i915_vma.c

674

for (n = 0; n < ARRAY_SIZE(view.rotated.plane); n++) {

sys/dev/pci/drm/include/drm/drm_atomic.h

1016

#define for_each_oldnew_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \

sys/dev/pci/drm/include/drm/drm_atomic.h

1021

((plane) = (__state)->planes[__i].ptr, \

sys/dev/pci/drm/include/drm/drm_atomic.h

1033

#define for_each_new_plane_in_state_reverse(__state, plane, new_plane_state, __i) \

sys/dev/pci/drm/include/drm/drm_atomic.h

1038

((plane) = (__state)->planes[__i].ptr, \

sys/dev/pci/drm/include/drm/drm_atomic.h

1052

#define for_each_old_plane_in_state(__state, plane, old_plane_state, __i) \

sys/dev/pci/drm/include/drm/drm_atomic.h

1057

((plane) = (__state)->planes[__i].ptr, \

sys/dev/pci/drm/include/drm/drm_atomic.h

1070

#define for_each_new_plane_in_state(__state, plane, new_plane_state, __i) \

sys/dev/pci/drm/include/drm/drm_atomic.h

1075

((plane) = (__state)->planes[__i].ptr, \

sys/dev/pci/drm/include/drm/drm_atomic.h

1076

(void)(plane) /* Only to avoid unused-but-set-variable warning */, \

sys/dev/pci/drm/include/drm/drm_atomic.h

601

struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_atomic.h

699

struct drm_plane *plane)

sys/dev/pci/drm/include/drm/drm_atomic.h

701

return state->planes[drm_plane_index(plane)].state;

sys/dev/pci/drm/include/drm/drm_atomic.h

714

struct drm_plane *plane)

sys/dev/pci/drm/include/drm/drm_atomic.h

716

return state->planes[drm_plane_index(plane)].old_state;

sys/dev/pci/drm/include/drm/drm_atomic.h

729

struct drm_plane *plane)

sys/dev/pci/drm/include/drm/drm_atomic.h

731

return state->planes[drm_plane_index(plane)].new_state;

sys/dev/pci/drm/include/drm/drm_atomic.h

825

struct drm_plane *plane)

sys/dev/pci/drm/include/drm/drm_atomic.h

827

if (state->planes[drm_plane_index(plane)].state)

sys/dev/pci/drm/include/drm/drm_atomic.h

828

return state->planes[drm_plane_index(plane)].state;

sys/dev/pci/drm/include/drm/drm_atomic.h

830

return plane->state;

sys/dev/pci/drm/include/drm/drm_atomic.h

993

#define for_each_oldnew_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \

sys/dev/pci/drm/include/drm/drm_atomic.h

998

((plane) = (__state)->planes[__i].ptr, \

sys/dev/pci/drm/include/drm/drm_atomic.h

999

(void)(plane) /* Only to avoid unused-but-set-variable warning */, \

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

149

int drm_atomic_helper_update_plane(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

157

int drm_atomic_helper_disable_plane(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

200

#define drm_atomic_crtc_for_each_plane(plane, crtc) \

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

201

drm_for_each_plane_mask(plane, (crtc)->dev, (crtc)->state->plane_mask)

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

213

#define drm_atomic_crtc_state_for_each_plane(plane, crtc_state) \

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

214

drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask)

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

231

#define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

232

drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask) \

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

235

plane)))

sys/dev/pci/drm/include/drm/drm_atomic_state_helper.h

57

struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_atomic_state_helper.h

58

void __drm_atomic_helper_plane_reset(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_atomic_state_helper.h

60

void drm_atomic_helper_plane_reset(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_atomic_state_helper.h

61

void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_atomic_state_helper.h

64

drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_atomic_state_helper.h

66

void drm_atomic_helper_plane_destroy_state(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_blend.h

45

int drm_plane_create_alpha_property(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_blend.h

46

int drm_plane_create_rotation_property(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_blend.h

52

int drm_plane_create_zpos_property(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_blend.h

55

int drm_plane_create_zpos_immutable_property(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_blend.h

59

int drm_plane_create_blend_mode_property(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_color_mgmt.h

88

int drm_plane_create_color_properties(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_fourcc.h

274

int plane)

sys/dev/pci/drm/include/drm/drm_fourcc.h

276

if (!info || plane >= info->num_planes)

sys/dev/pci/drm/include/drm/drm_fourcc.h

279

if (plane == 0)

sys/dev/pci/drm/include/drm/drm_fourcc.h

296

int plane)

sys/dev/pci/drm/include/drm/drm_fourcc.h

298

if (!info || plane >= info->num_planes)

sys/dev/pci/drm/include/drm/drm_fourcc.h

301

if (plane == 0)

sys/dev/pci/drm/include/drm/drm_fourcc.h

317

int plane);

sys/dev/pci/drm/include/drm/drm_fourcc.h

319

int plane);

sys/dev/pci/drm/include/drm/drm_fourcc.h

320

unsigned int drm_format_info_bpp(const struct drm_format_info *info, int plane);

sys/dev/pci/drm/include/drm/drm_fourcc.h

322

int plane, unsigned int buffer_width);

sys/dev/pci/drm/include/drm/drm_gem_framebuffer_helper.h

20

unsigned int plane);

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1255

int (*prepare_fb)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1266

void (*cleanup_fb)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1289

int (*begin_fb_access)(struct drm_plane *plane, struct drm_plane_state *new_plane_state);

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1297

void (*end_fb_access)(struct drm_plane *plane, struct drm_plane_state *new_plane_state);

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1334

int (*atomic_check)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1351

void (*atomic_update)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1376

void (*atomic_enable)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1401

void (*atomic_disable)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1425

int (*atomic_async_check)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1462

void (*atomic_async_update)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1485

int (*get_scanout_buffer)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1501

void (*panic_flush)(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1509

static inline void drm_plane_helper_add(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h

1512

plane->helper_private = funcs;

sys/dev/pci/drm/include/drm/drm_plane.h

1003

int drm_plane_create_scaling_filter_property(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

1005

int drm_plane_add_size_hints_property(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

319

int (*update_plane)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

342

int (*disable_plane)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

352

void (*destroy)(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_plane.h

364

void (*reset)(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_plane.h

380

int (*set_property)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

414

struct drm_plane_state *(*atomic_duplicate_state)(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_plane.h

424

void (*atomic_destroy_state)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

469

int (*atomic_set_property)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

492

int (*atomic_get_property)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

509

int (*late_register)(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_plane.h

520

void (*early_unregister)(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_plane.h

550

bool (*format_mod_supported)(struct drm_plane *plane, uint32_t format,

sys/dev/pci/drm/include/drm/drm_plane.h

56

struct drm_plane *plane;

sys/dev/pci/drm/include/drm/drm_plane.h

566

bool (*format_mod_supported_async)(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

812

struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

820

void drm_plane_cleanup(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_plane.h

918

static inline unsigned int drm_plane_index(const struct drm_plane *plane)

sys/dev/pci/drm/include/drm/drm_plane.h

920

return plane->index;

sys/dev/pci/drm/include/drm/drm_plane.h

927

static inline u32 drm_plane_mask(const struct drm_plane *plane)

sys/dev/pci/drm/include/drm/drm_plane.h

929

return 1 << drm_plane_index(plane);

sys/dev/pci/drm/include/drm/drm_plane.h

933

void drm_plane_force_disable(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_plane.h

935

int drm_mode_plane_set_obj_prop(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

965

#define drm_for_each_plane_mask(plane, dev, plane_mask) \

sys/dev/pci/drm/include/drm/drm_plane.h

966

list_for_each_entry((plane), &(dev)->mode_config.plane_list, head) \

sys/dev/pci/drm/include/drm/drm_plane.h

967

for_each_if ((plane_mask) & drm_plane_mask(plane))

sys/dev/pci/drm/include/drm/drm_plane.h

978

#define drm_for_each_legacy_plane(plane, dev) \

sys/dev/pci/drm/include/drm/drm_plane.h

979

list_for_each_entry(plane, &(dev)->mode_config.plane_list, head) \

sys/dev/pci/drm/include/drm/drm_plane.h

980

for_each_if (plane->type == DRM_PLANE_TYPE_OVERLAY)

sys/dev/pci/drm/include/drm/drm_plane.h

989

#define drm_for_each_plane(plane, dev) \

sys/dev/pci/drm/include/drm/drm_plane.h

990

list_for_each_entry(plane, &(dev)->mode_config.plane_list, head)

sys/dev/pci/drm/include/drm/drm_plane.h

992

bool drm_plane_has_format(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane.h

997

void drm_plane_enable_fb_damage_clips(struct drm_plane *plane);

sys/dev/pci/drm/include/drm/drm_plane_helper.h

34

int drm_plane_helper_update_primary(struct drm_plane *plane, struct drm_crtc *crtc,

sys/dev/pci/drm/include/drm/drm_plane_helper.h

41

int drm_plane_helper_disable_primary(struct drm_plane *plane,

sys/dev/pci/drm/include/drm/drm_plane_helper.h

43

void drm_plane_helper_destroy(struct drm_plane *plane);

sys/sys/videoio.h

4857

u_int32_t plane;