sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2255
pr_info("switched on\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2261
pr_info("debug: VM handling debug enabled\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2266
pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2271
pr_info("debug: soft reset for GPU recovery disabled\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2276
pr_info("debug: place fw in vram for frontdoor loading\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2281
pr_info("debug: enable RAS ACA\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2286
pr_info("debug: enable experimental reset features\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2291
pr_info("debug: ring reset disabled\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2295
pr_info("debug: use vram for smu pool\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2299
pr_info("debug: VM mode debug for userptr is enabled\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2304
pr_info("debug: disable kernel logs of correctable errors\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2309
pr_info("debug: allowing command submission to CE engine\n");
sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c
554
pr_info("Detected AMDGPU %s Counters. # of Counters = %d.\n",
sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c
557
pr_info("Detected AMDGPU %d Perf Events.\n", total_num_events);
sys/dev/pci/drm/amd/amdgpu/atom.c
1042
pr_info("Bad case\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
1466
pr_info("ATOM BIOS: %s\n", ctx->vbios_pn);
sys/dev/pci/drm/amd/amdgpu/atom.c
1539
pr_info("Invalid BIOS magic\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
1546
pr_info("Invalid ATI magic\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
1555
pr_info("Invalid ATOM magic\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
177
pr_info("Unknown IIO opcode\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
201
pr_info("PCI registers are not implemented\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
204
pr_info("SYSIO registers are not implemented\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
208
pr_info("Bad IO mode\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
212
pr_info("Undefined indirect IO read method %d\n",
sys/dev/pci/drm/amd/amdgpu/atom.c
230
pr_info("PS index out of range: %i > %i\n", idx, ctx->ps_size);
sys/dev/pci/drm/amd/amdgpu/atom.c
271
pr_info("WS index out of range: %i > %i\n", idx, ctx->ws_size);
sys/dev/pci/drm/amd/amdgpu/atom.c
482
pr_info("PCI registers are not implemented\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
485
pr_info("SYSIO registers are not implemented\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
489
pr_info("Bad IO mode\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
493
pr_info("Undefined indirect IO write method %d\n",
sys/dev/pci/drm/amd/amdgpu/atom.c
506
pr_info("PS index out of range: %i > %i\n", idx, ctx->ps_size);
sys/dev/pci/drm/amd/amdgpu/atom.c
542
pr_info("WS index out of range: %i > %i\n", idx, ctx->ws_size);
sys/dev/pci/drm/amd/amdgpu/atom.c
869
pr_info("unimplemented!\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
874
pr_info("unimplemented!\n");
sys/dev/pci/drm/amd/amdgpu/atom.c
879
pr_info("unimplemented!\n");
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
1961
pr_info("IO link not available for non x86 platforms\n");
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
1976
pr_info("Virtual CRAT table created for CPU\n");
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
2380
pr_info("Virtual CRAT table created for GPU\n");
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
288
pr_info(
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1548
pr_info("SW scheduler is used");
sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c
1076
pr_info("HMM registered %ldMB device memory\n", size >> 20);
sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c
72
pr_info("Cannot open more queues for process with pid %d\n",
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
340
pr_info("SVM mapping failed, exceeds resident system memory limit\n");
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
936
pr_info("Topology: Add APU node [0x%0x:0x%0x]\n",
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
940
pr_info("Topology: Add CPU node\n");
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
942
pr_info("Topology: Add dGPU node [0x%0x:0x%0x]\n",
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
429
pr_info("%s", msg);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
453
pr_info("%pV", &vaf);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
504
pr_info("%s", msg);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
66
if (dpcd_caps->pr_info.pixel_deviation_per_line == 0 ||
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
67
dpcd_caps->pr_info.max_deviation_line == 0)
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1282
struct replay_info pr_info;
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
168
copy_settings_data->pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line;
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
169
copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2175
&link->dpcd_caps.pr_info.pixel_deviation_per_line,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2176
sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line));
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2178
&link->dpcd_caps.pr_info.max_deviation_line,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2179
sizeof(link->dpcd_caps.pr_info.max_deviation_line));
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
1010
max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
1011
pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2977
pr_info("manual fan speed control should be enabled first\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
107
pr_info("dpm has been disabled\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
87
pr_info("dpm has been enabled\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
202
pr_info("hwmgr_sw_init smu backed is %s\n", hwmgr->smumgr_funcs->name);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c
230
pr_info("dpm not supported \n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
378
pr_info("Invalid VBIOS AVFS ProfilingInfo Revision!\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
397
pr_info("Error retrieving BIOS smu_info Table Address!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
522
pr_info("Error retrieving BIOS firmwareinfo!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
535
pr_info("Fw info table revision does not match!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
553
pr_info("Error retrieving BIOS Table Address!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
396
pr_info("restore the fine grain parameters\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
635
pr_info("smu firmware version too old, can not set dpm level\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
76
pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
986
pr_info("Currently sclk only support 3 levels on RV\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2094
pr_info("Error retrieving EVV voltage value!\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2162
pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2645
pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2977
pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4433
pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4435
pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5462
pr_info("OD voltage is out of range [%d - %d] mV\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5471
pr_info("OD engine clock is out of range [%d - %d] MHz\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5479
pr_info("OD memory clock is out of range [%d - %d] MHz\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5508
pr_info("OverDrive feature not enabled\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5537
pr_info("invalid clock voltage input \n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
1582
pr_info("Populate LClock Level %d Failed!\n", i);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
1595
pr_info("Populate LClock Level %d Failed!\n", i);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2388
pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2740
pr_info("THERMAL Feature Already enabled!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2760
pr_info("THERMAL Feature Already disabled!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3015
pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3307
pr_info("VI should always have 2 performance levels");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3616
pr_info("DPM Table Has Too Many Entries!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4060
pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4135
pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4322
pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5428
pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5436
pr_info("OD engine clock is out of range [%d - %d] MHz\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5445
pr_info("OD memory clock is out of range [%d - %d] MHz\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5608
pr_info("OverDrive feature not enabled\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5638
pr_info("invalid clock voltage input\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
633
pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
806
pr_info("Number of Pcie Entries exceed the number of"
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
558
pr_info("Failed to update Fan Control Table in PPTable!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
583
pr_info("Failed to update fan control table in pptable!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
589
pr_info("Attempt to disable SMC fan control feature failed!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
595
pr_info("Attempt to enable SMC fan control feature failed!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1401
pr_info("Failed to export SMU metrics table!\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1598
pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1647
pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2131
pr_info("Failed to export SMU metrics table!\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2323
pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2374
pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2988
pr_info("Sclk min/max frequency overdrive not supported\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2994
pr_info("invalid number of input parameters %d\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3003
pr_info("Invalid index %d\n", input_index);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3004
pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3010
pr_info("clock freq %d is not within allowed range [%d - %d]\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3031
pr_info("Mclk max frequency overdrive not supported\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3037
pr_info("invalid number of input parameters %d\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3046
pr_info("Invalid index %d\n", input_index);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3047
pr_info("Support max Mclk frequency setting only which index by 1\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3053
pr_info("clock freq %d is not within allowed range [%d - %d]\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3075
pr_info("Voltage curve calibrate not supported\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3081
pr_info("invalid number of input parameters %d\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3091
pr_info("Setting for point %d is not supported\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3093
pr_info("Three supported points index by 0, 1, 2\n");
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3100
pr_info("clock freq %d is not within allowed range [%d - %d]\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3110
pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
996
pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
998
pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c
76
pr_info("Unmatch PPTable version: "
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1923
pr_info("VDDCshould be on SVI2 controller!");
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2355
pr_info("smc is running, no need to load smc firmware\n");
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
396
pr_info("Engine clock can't satisfy stutter requirement!\n");
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
207
pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
104
pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
187
pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
747
pr_info("smu version %02d.%02d.%02d\n",
sys/dev/pci/drm/apple/parser.c
515
pr_info("dcp: rejecting mode %lldx%lld@%lld.%03lld (pixel clk:%d)\n",
sys/dev/pci/drm/drm_ioctl.c
358
pr_info("broken atomic modeset userspace detected, disabling atomic\n");
sys/dev/pci/drm/drm_privacy_screen_x86.c
91
pr_info("Found '%s' privacy-screen provider\n",
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c
377
pr_info("Purging GPU memory, %lu pages freed, "
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1326
pr_info("%s missing THP support, skipping\n", __func__);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1426
pr_info("%s unable to allocate huge-page(s) with size=%u, i=%d\n",
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1507
pr_info("Device lacks local memory, skipping\n");
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1567
pr_info("device lacks compact 64K page support, skipping\n");
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1572
pr_info("device lacks LMEM support, skipping\n");
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1586
pr_info("LMEM compact unable to allocate huge-page(s)\n");
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1637
pr_info("device lacks PS64, skipping\n");
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1847
pr_info("missing THP support, skipping\n");
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1886
pr_info("failed to allocate THP, finishing test early\n");
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
2026
pr_info("PPGTT not supported, skipping live-selftests\n");
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
575
pr_info("Using hole at %llx\n", t->hole);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
337
pr_info("%s: using %s\n", __func__, ctx.engine->name);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
105
pr_info("Populated %d contexts on %s in %lluns\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1152
pr_info("RPCS=0x%x; %u%sx%u%s\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1286
pr_info("%s: SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1460
pr_info("Submitted %lu dwords (across %lu engines)\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
170
pr_info("Switch latencies on %s: 1 = %lluns, %lu = %lluns\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1885
pr_info("Checked %lu scratch offsets across %lu engines\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
235
pr_info("%s: %lu switches (sync) <%d>\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
278
pr_info("%s: %lu switches (many) <%d>\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
754
pr_info("Submitted %lu contexts to %s, filling %lu dwords\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
887
pr_info("Submitted %lu contexts to %s, filling %lu dwords\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
298
pr_info("Simulated failure modes: gpu: %d, alloc:%d, ban_memcpy: %d\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
456
pr_info("Simulated failure modes: gpu: %d, alloc: %d, ban_memcpy: %d\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1086
pr_info("%s filled=%lluMiB\n", __func__, total >> 20);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1101
pr_info("igt_mmap(%s, %d) @ %lx\n",
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
531
pr_info("%s: Completed %lu trials\n", __func__, count);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3601
pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3630
pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3821
pr_info("Requestx%d latencies on %s: 1 = %lluns, %lu = %lluns\n",
sys/dev/pci/drm/i915/gt/selftest_gt_pm.c
112
pr_info("%s: TIMESTAMP %d cycles [%lldns] in %lldns [%d cycles], using CS clock frequency of %uKHz\n",
sys/dev/pci/drm/i915/gt/selftest_gt_pm.c
88
pr_info("CS_TIMESTAMP frequency unknown\n");
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1172
pr_info("i915_reset_engine(%s:%s): %lu resets\n",
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1768
pr_info("%s: Completed %d queued resets\n",
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
414
pr_info("%s: %d resets\n", __func__, count);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
522
pr_info("%s(%s): %d resets\n", __func__, engine->name, count);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
669
pr_info("%s(%s): %d resets\n", __func__, engine->name, count);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
819
pr_info("%s: Completed %lu %s resets\n",
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1929
pr_info("%s: pphwsp runtime %lluns, average %lluns\n",
sys/dev/pci/drm/i915/gt/selftest_lrc.c
259
pr_info("%s: HW register image:\n", engine->name);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
262
pr_info("%s: SW register image:\n", engine->name);
sys/dev/pci/drm/i915/gt/selftest_migrate.c
543
pr_info("%s\n", __func__);
sys/dev/pci/drm/i915/gt/selftest_migrate.c
636
pr_info("%s emit=%u sz=%d\n", __func__, rq->ring->emit, sz);
sys/dev/pci/drm/i915/gt/selftest_migrate.c
649
pr_info("%s emite_pte ring space=%u\n", __func__, rq->ring->space);
sys/dev/pci/drm/i915/gt/selftest_migrate.c
876
pr_info("%s: %zd KiB fill: %lld MiB/s\n",
sys/dev/pci/drm/i915/gt/selftest_migrate.c
959
pr_info("%s: %zd KiB copy: %lld MiB/s\n",
sys/dev/pci/drm/i915/gt/selftest_rc6.c
127
pr_info("GPU consumed %lluuW in RC0 and %lluuW in RC6\n",
sys/dev/pci/drm/i915/gt/selftest_reset.c
163
pr_info("%s reset clobbered %ld pages of stolen, last clobber at page %ld\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
1204
pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
1260
pr_info("RPS has interrupt support\n");
sys/dev/pci/drm/i915/gt/selftest_rps.c
1262
pr_info("RPS has timer support\n");
sys/dev/pci/drm/i915/gt/selftest_rps.c
1302
pr_info("%s: dynamically reclocked to %u:%uMHz while busy in %lluns, and %u:%uMHz while idle in %lluns\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
207
pr_info("P_STATE_CAP[%x]: 0x%08x\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
212
pr_info("P_STATE_LIMITS[%x]: 0x%08x\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
333
pr_info("%s: rps counted %d C0 cycles [%lldns] in %lldns [%d cycles], using GT clock frequency of %uKHz\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
473
pr_info("%s: range:[%x:%uMHz, %x:%uMHz] limit:[%x:%uMHz], %x:%x response %lluns:%lluns\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
524
pr_info("%5s %5s %5s\n", "GPU", "eCPU", "eRing");
sys/dev/pci/drm/i915/gt/selftest_rps.c
531
pr_info("%5d %5d %5d\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
681
pr_info("%s: min:%lluKHz @ %uMHz, max:%lluKHz @ %uMHz [%d%%]\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
707
pr_info("%s: %x:%uMHz: %lluKHz [%d%%]\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
819
pr_info("%s: min:%lluKHz @ %uMHz, max:%lluKHz @ %uMHz [%d%%]\n",
sys/dev/pci/drm/i915/gt/selftest_rps.c
845
pr_info("%s: %x:%uMHz: %lluKHz [%d%%]\n",
sys/dev/pci/drm/i915/gt/selftest_slpc.c
227
pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n",
sys/dev/pci/drm/i915/gt/selftest_slpc.c
271
pr_info("Pcode throttled frequency 0x%x\n", perf_limit_reasons);
sys/dev/pci/drm/i915/gt/selftest_slpc.c
390
pr_info("Max actual frequency for %s was %d\n",
sys/dev/pci/drm/i915/gt/selftest_timeline.c
1159
pr_info("%s: simulated %lu wraps\n", engine->name, count);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
333
pr_info("%s: %lu random insertions, %lluns/insert\n",
sys/dev/pci/drm/i915/gt/selftest_timeline.c
351
pr_info("%s: %lu random lookups, %lluns/lookup\n",
sys/dev/pci/drm/i915/gt/selftest_timeline.c
367
pr_info("%s: %lu in-order insertions, %lluns/insert\n",
sys/dev/pci/drm/i915/gt/selftest_timeline.c
381
pr_info("%s: %lu in-order lookups, %lluns/lookup\n",
sys/dev/pci/drm/i915/gt/selftest_timeline.c
405
pr_info("%s: %lu repeated insert/lookups, %lluns/op\n",
sys/dev/pci/drm/i915/gt/selftest_timeline.c
433
pr_info("%s: %lu cyclic/%d insert/lookups, %lluns/op\n",
sys/dev/pci/drm/i915/gt/selftest_tlb.c
94
pr_info("%s(%s): Sampling %llx, with alignment %llx, using PTE size %x (phys %x, sg %x), invalidate:%llx+%llx\n",
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1211
pr_info("Verifying after GPU reset...\n");
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1266
pr_info("Verifying after %s reset...\n", engine->name);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
196
pr_info("RING_NONPRIV[%d]: expected 0x%08x, found 0x%08x\n",
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
307
pr_info("Checking %d whitelisted registers on %s (RING_NONPRIV) [%s]\n",
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
696
pr_info("%s: Whitelisted read-only register: %x, original value %08x\n",
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
699
pr_info("%s: Whitelisted register: %x, original value %08x, rsvd %08x\n",
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
711
pr_info("Wrote %08x, read %08x, expect %08x\n",
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
722
pr_info("Wrote %08x, read %08x, expect %08x\n",
sys/dev/pci/drm/i915/selftests/i915_gem_evict.c
446
pr_info("Filled GGTT with %lu 1MiB nodes\n", count);
sys/dev/pci/drm/i915/selftests/i915_gem_evict.c
495
pr_info("Submitted %lu contexts/requests on %s\n",
sys/dev/pci/drm/i915/selftests/i915_perf.c
266
pr_info("CPU delay: %lluns, expected %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_perf.c
272
pr_info("GPU delay: %uns, expected %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
1103
pr_info("Batch latencies on %s: 1 = %lluns, %lu = %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
1497
pr_info("%s: %lu request + sync\n", engine->name, count);
sys/dev/pci/drm/i915/selftests/i915_request.c
1526
pr_info("%s: %lu requests\n", engine->name, count);
sys/dev/pci/drm/i915/selftests/i915_request.c
1852
pr_info("Completed %lu waits for %lu fences across %d engines and %d cpus\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2078
pr_info("%s: semaphore response %d cycles, %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2149
pr_info("%s: idle dispatch latency %d cycles, %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2226
pr_info("%s: busy dispatch latency %d cycles, %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2339
pr_info("%s: inter-request latency %d cycles, %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2434
pr_info("%s: context switch latency %d cycles, %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2537
pr_info("%s: preemption dispatch latency %d cycles, %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2545
pr_info("%s: preemption switch latency %d cycles, %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2639
pr_info("%s: completion latency %d cycles, %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
2932
pr_info("%s %5s: { seqno:%d, busy:%d.%02d%%, runtime:%lldms, walltime:%lldms }\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
3278
pr_info("%s %5s: { count:%lu, busy:%d.%02d%%, runtime:%lldms, walltime:%lldms }\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
524
pr_info("Completed %lu waits for %lu fence across %d cpus\n",
sys/dev/pci/drm/i915/selftests/i915_request.c
633
pr_info("Request latencies on %s: 1 = %lluns, %lu = %lluns\n",
sys/dev/pci/drm/i915/selftests/i915_selftest.c
200
pr_info(DRIVER_NAME ": Performing %s selftests with st_random_seed=0x%x st_timeout=%u\n",
sys/dev/pci/drm/i915/selftests/i915_selftest.c
212
pr_info(DRIVER_NAME ": Running %s\n", st->name);
sys/dev/pci/drm/i915/selftests/i915_selftest.c
43
pr_info(DRIVER_NAME ": %s() - ok!\n", __func__);
sys/dev/pci/drm/i915/selftests/i915_selftest.c
444
pr_info(DRIVER_NAME ": Running %s/%s\n", caller, st->name);
sys/dev/pci/drm/i915/selftests/i915_selftest.c
489
pr_info("*\n");
sys/dev/pci/drm/i915/selftests/i915_selftest.c
49
pr_info("%s: %s() - ok!\n", i915->drm.driver->name, __func__);
sys/dev/pci/drm/i915/selftests/i915_selftest.c
499
pr_info("[%04zx] %s\n", pos, line);
sys/dev/pci/drm/i915/selftests/igt_mmap.c
30
pr_info("Failed to lookup %llx\n", offset);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1039
pr_info("%s: using %s\n", __func__, engine->name);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1277
pr_info("%s src(%s, %s) -> dst(%s, %s) %14s %4llu KiB copy: %5lld MiB/s\n",
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1385
pr_info("device lacks LMEM support, skipping\n");
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
573
pr_info("%s with ps=%llx, io_size=%llx, total=%llx\n",
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
602
pr_info("%s mappable theft=(%lluMiB/%lluMiB), total=%lluMiB\n",
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
817
pr_info("%s not enough lmem for ps(%u) err=%d\n",
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
836
pr_info("%s not enough lmem for ps(%u) err=%d\n",
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
942
pr_info("%s completed (%u) iterations\n", __func__, i);
sys/dev/pci/drm/radeon/atom.c
1009
pr_info("Bad case\n");
sys/dev/pci/drm/radeon/atom.c
1043
pr_info("unimplemented!\n");
sys/dev/pci/drm/radeon/atom.c
1300
pr_info("Invalid BIOS magic\n");
sys/dev/pci/drm/radeon/atom.c
1307
pr_info("Invalid ATI magic\n");
sys/dev/pci/drm/radeon/atom.c
1316
pr_info("Invalid ATOM magic\n");
sys/dev/pci/drm/radeon/atom.c
1340
pr_info("ATOM BIOS: %s\n", name);
sys/dev/pci/drm/radeon/atom.c
179
pr_info("Unknown IIO opcode\n");
sys/dev/pci/drm/radeon/atom.c
203
pr_info("PCI registers are not implemented\n");
sys/dev/pci/drm/radeon/atom.c
206
pr_info("SYSIO registers are not implemented\n");
sys/dev/pci/drm/radeon/atom.c
210
pr_info("Bad IO mode\n");
sys/dev/pci/drm/radeon/atom.c
214
pr_info("Undefined indirect IO read method %d\n",
sys/dev/pci/drm/radeon/atom.c
232
pr_info("PS index out of range: %i > %i\n", idx, ctx->ps_size);
sys/dev/pci/drm/radeon/atom.c
273
pr_info("WS index out of range: %i > %i\n", idx, ctx->ws_size);
sys/dev/pci/drm/radeon/atom.c
485
pr_info("PCI registers are not implemented\n");
sys/dev/pci/drm/radeon/atom.c
488
pr_info("SYSIO registers are not implemented\n");
sys/dev/pci/drm/radeon/atom.c
492
pr_info("Bad IO mode\n");
sys/dev/pci/drm/radeon/atom.c
496
pr_info("Undefined indirect IO write method %d\n",
sys/dev/pci/drm/radeon/atom.c
509
pr_info("PS index out of range: %i > %i\n", idx, ctx->ps_size);
sys/dev/pci/drm/radeon/atom.c
545
pr_info("WS index out of range: %i > %i\n", idx, ctx->ws_size);
sys/dev/pci/drm/radeon/atom.c
836
pr_info("unimplemented!\n");
sys/dev/pci/drm/radeon/atom.c
841
pr_info("unimplemented!\n");
sys/dev/pci/drm/radeon/atom.c
846
pr_info("unimplemented!\n");
sys/dev/pci/drm/radeon/evergreen_cs.c
2870
pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);
sys/dev/pci/drm/radeon/evergreen_cs.c
3309
pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);
sys/dev/pci/drm/radeon/r600_cs.c
2331
pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);
sys/dev/pci/drm/radeon/r600_cs.c
2537
pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);
sys/dev/pci/drm/radeon/radeon.h
2552
#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
sys/dev/pci/drm/radeon/radeon_device.c
1236
pr_info("radeon: switched on\n");
sys/dev/pci/drm/radeon/radeon_device.c
1245
pr_info("radeon: switched off\n");
sys/dev/usb/dwc2/dwc2_core.h
1276
pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
