sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

157

amdgpu_gem_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1130

panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1131

panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1132

panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1133

panel_config->pps.extra_post_t7_ms = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1134

panel_config->pps.extra_pre_t11_ms = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1135

panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1136

panel_config->pps.extra_post_OUI_ms = 0;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1203

} pps;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

193

dsc_log_pps(dsc, &dsc20->reg_vals.pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

212

drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

213

dsc_log_pps(dsc, &dsc_reg_vals.pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

281

void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

284

int bits_per_pixel = pps->bits_per_pixel;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

286

DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

287

DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

288

DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

289

DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

290

DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

291

DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

292

DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

293

DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

295

DC_LOG_DSC("\tpic_height %d", pps->pic_height);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

296

DC_LOG_DSC("\tpic_width %d", pps->pic_width);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

297

DC_LOG_DSC("\tslice_height %d", pps->slice_height);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

298

DC_LOG_DSC("\tslice_width %d", pps->slice_width);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

299

DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

300

DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

301

DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

302

DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

303

DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

304

DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

305

DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

306

DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

307

DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

308

DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

309

DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

310

DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

311

DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

313

DC_LOG_DSC("\tnative_420 %d", pps->native_420);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

314

DC_LOG_DSC("\tnative_422 %d", pps->native_422);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

315

DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

316

DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

317

DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

318

DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

319

DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

320

DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

321

DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

322

DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

323

DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

326

DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

329

DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

330

DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

331

DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

400

dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

401

dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

402

dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

403

dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

404

dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

405

dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

406

dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

410

dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

413

dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

415

ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

416

if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

423

dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

425

dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

427

dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

428

dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

429

dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

430

dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

432

calc_rc_params(&rc, &dsc_reg_vals->pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

437

if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &rc, &dsc_params)) {

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

445

dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

531

reg_vals->pps.dsc_version_minor = 2;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

532

reg_vals->pps.dsc_version_major = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

533

reg_vals->pps.line_buf_depth = 9;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

534

reg_vals->pps.bits_per_component = 8;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

535

reg_vals->pps.block_pred_enable = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

536

reg_vals->pps.slice_chunk_size = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

537

reg_vals->pps.pic_width = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

538

reg_vals->pps.pic_height = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

539

reg_vals->pps.slice_width = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

540

reg_vals->pps.slice_height = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

541

reg_vals->pps.initial_xmit_delay = 170;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

542

reg_vals->pps.initial_dec_delay = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

543

reg_vals->pps.initial_scale_value = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

544

reg_vals->pps.scale_increment_interval = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

545

reg_vals->pps.scale_decrement_interval = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

546

reg_vals->pps.nfl_bpg_offset = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

547

reg_vals->pps.slice_bpg_offset = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

548

reg_vals->pps.nsl_bpg_offset = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

549

reg_vals->pps.initial_offset = 6144;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

550

reg_vals->pps.final_offset = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

551

reg_vals->pps.flatness_min_qp = 3;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

552

reg_vals->pps.flatness_max_qp = 12;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

553

reg_vals->pps.rc_model_size = 8192;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

554

reg_vals->pps.rc_edge_factor = 6;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

555

reg_vals->pps.rc_quant_incr_limit0 = 11;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

556

reg_vals->pps.rc_quant_incr_limit1 = 11;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

557

reg_vals->pps.rc_tgt_offset_low = 3;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

558

reg_vals->pps.rc_tgt_offset_high = 3;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

569

reg_vals->pps = dsc_params->pps;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

573

reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

592

DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

595

PIC_WIDTH, reg_vals->pps.pic_width,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

596

PIC_HEIGHT, reg_vals->pps.pic_height);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

625

DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

626

LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

627

DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

638

BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

641

CHUNK_SIZE, reg_vals->pps.slice_chunk_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

644

PIC_WIDTH, reg_vals->pps.pic_width,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

645

PIC_HEIGHT, reg_vals->pps.pic_height);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

648

SLICE_WIDTH, reg_vals->pps.slice_width,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

649

SLICE_HEIGHT, reg_vals->pps.slice_height);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

652

INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

655

INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

656

SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

659

SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

660

FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

661

SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

664

NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

665

SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

668

NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

669

SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

672

INITIAL_OFFSET, reg_vals->pps.initial_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

673

FINAL_OFFSET, reg_vals->pps.final_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

676

FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

677

FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

678

RC_MODEL_SIZE, reg_vals->pps.rc_model_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

681

RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

682

RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

683

RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

684

RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

685

RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

688

RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

689

RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

690

RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

691

RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

694

RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

695

RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

696

RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

697

RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

700

RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

701

RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

702

RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

703

RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

706

RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

707

RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

708

RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

709

RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

710

RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

713

RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

714

RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

715

RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

716

RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

717

RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

718

RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

721

RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

722

RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

723

RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

724

RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

725

RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

726

RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

729

RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

730

RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

731

RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

732

RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

733

RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

734

RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

737

RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

738

RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

739

RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

740

RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

741

RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

742

RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

745

RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

746

RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

747

RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

748

RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

749

RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

750

RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

753

RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

754

RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

755

RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

756

RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

757

RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

758

RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

761

RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

762

RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

763

RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

764

RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

765

RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

766

RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

541

struct drm_dsc_config pps;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

576

struct drm_dsc_config *pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

134

dsc_log_pps(dsc, &dsc401->reg_vals.pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

213

DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

246

DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

247

LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

248

DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

259

BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

262

CHUNK_SIZE, reg_vals->pps.slice_chunk_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

265

PIC_WIDTH, reg_vals->pps.pic_width,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

266

PIC_HEIGHT, reg_vals->pps.pic_height);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

269

SLICE_WIDTH, reg_vals->pps.slice_width,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

270

SLICE_HEIGHT, reg_vals->pps.slice_height);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

273

INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

276

INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

277

SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

280

SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

281

FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

282

SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

285

NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

286

SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

289

NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

290

SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

293

INITIAL_OFFSET, reg_vals->pps.initial_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

294

FINAL_OFFSET, reg_vals->pps.final_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

297

FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

298

FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

299

RC_MODEL_SIZE, reg_vals->pps.rc_model_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

302

RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

303

RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

304

RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

305

RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

306

RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

309

RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

310

RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

311

RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

312

RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

315

RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

316

RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

317

RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

318

RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

321

RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

322

RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

323

RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

324

RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

327

RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

328

RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

329

RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

330

RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

331

RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

334

RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

335

RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

336

RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

337

RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

338

RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

339

RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

342

RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

343

RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

344

RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

345

RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

346

RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

347

RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

350

RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

351

RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

352

RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

353

RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

354

RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

355

RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

358

RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

359

RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

360

RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

361

RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

362

RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

363

RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

366

RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

367

RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

368

RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

369

RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

370

RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

371

RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

374

RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

375

RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

376

RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

377

RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

378

RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

379

RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

382

RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

383

RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

384

RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

385

RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

386

RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

387

RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);

sys/dev/pci/drm/amd/display/dc/dsc/dscc_types.h

42

struct drm_dsc_config pps;

sys/dev/pci/drm/amd/display/dc/dsc/dscc_types.h

51

int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

40

void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps)

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

46

u16 drm_bpp = pps->bits_per_pixel;

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

47

int slice_width = pps->slice_width;

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

48

int slice_height = pps->slice_height;

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

50

mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 :

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

51

(pps->native_422 ? CM_422 :

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

52

pps->native_420 ? CM_420 : CM_444));

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

53

bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10)

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

56

is_navite_422_or_420 = pps->native_422 || pps->native_420;

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c

61

pps->dsc_version_minor);

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.h

32

void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps);

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c

105

dsc_params->pps = *pps;

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c

106

dsc_params->pps.initial_scale_value = 8 * rc->rc_model_size / (rc->rc_model_size - rc->initial_fullness_offset);

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c

108

copy_pps_fields(&dsc_cfg, &dsc_params->pps);

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c

111

dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64;

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c

118

copy_pps_fields(&dsc_params->pps, &dsc_cfg);

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c

98

int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1046

post_T7_delay += link->panel_config.pps.extra_post_t7_ms;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1072

pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

748

if (link->panel_config.pps.extra_t3_ms > 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

749

int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

832

link->panel_config.pps.extra_t12_ms;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

938

t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2108

post_oui_delay += link->panel_config.pps.extra_post_OUI_ms;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

451

if (link && link->panel_config.pps.extra_delay_backlight_off > 0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

452

fsleep(link->panel_config.pps.extra_delay_backlight_off * 1000);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

509

if (link && link->panel_config.pps.extra_t7_ms > 0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

510

fsleep(link->panel_config.pps.extra_t7_ms * 1000);

sys/dev/pci/drm/drm_gem.c

135

entry->start), vaddr, pps, npages, centeridx,

sys/dev/pci/drm/drm_gem.c

91

drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,

sys/dev/pci/drm/drm_gem_dma_helper.c

187

off_t offset, vaddr_t vaddr, vm_page_t *pps, int npages, int centeridx,

sys/dev/pci/drm/drm_gem_dma_helper.c

205

if (pps[lcv] == PGO_DONTCARE)

sys/dev/pci/drm/drm_mipi_dsi.c

1569

const struct drm_dsc_picture_parameter_set *pps)

sys/dev/pci/drm/drm_mipi_dsi.c

1578

ret = mipi_dsi_picture_parameter_set(dsi, pps);

sys/dev/pci/drm/drm_mipi_dsi.c

730

const struct drm_dsc_picture_parameter_set *pps)

sys/dev/pci/drm/drm_mipi_dsi.c

735

.tx_len = sizeof(*pps),

sys/dev/pci/drm/drm_mipi_dsi.c

736

.tx_buf = pps,

sys/dev/pci/drm/i915/display/g4x_dp.c

460

drm_msleep(intel_dp->pps.panel_power_down_delay);

sys/dev/pci/drm/i915/display/intel_bios.c

1408

static void vbt_edp_to_pps_delays(struct intel_pps_delays *pps,

sys/dev/pci/drm/i915/display/intel_bios.c

1411

pps->power_up = edp_pps->t1_t3;

sys/dev/pci/drm/i915/display/intel_bios.c

1412

pps->backlight_on = edp_pps->t8;

sys/dev/pci/drm/i915/display/intel_bios.c

1413

pps->backlight_off = edp_pps->t9;

sys/dev/pci/drm/i915/display/intel_bios.c

1414

pps->power_down = edp_pps->t10;

sys/dev/pci/drm/i915/display/intel_bios.c

1415

pps->power_cycle = edp_pps->t11_t12;

sys/dev/pci/drm/i915/display/intel_bios.c

1445

vbt_edp_to_pps_delays(&panel->vbt.edp.pps,

sys/dev/pci/drm/i915/display/intel_bios.c

1699

const struct mipi_pps_data *pps;

sys/dev/pci/drm/i915/display/intel_bios.c

1724

pps = &start->pps[panel_type];

sys/dev/pci/drm/i915/display/intel_bios.c

1731

panel->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);

sys/dev/pci/drm/i915/display/intel_bios.c

1732

if (!panel->vbt.dsi.pps) {

sys/dev/pci/drm/i915/display/intel_bios.c

3316

kfree(panel->vbt.dsi.pps);

sys/dev/pci/drm/i915/display/intel_bios.c

3317

panel->vbt.dsi.pps = NULL;

sys/dev/pci/drm/i915/display/intel_display_core.h

512

} pps;

sys/dev/pci/drm/i915/display/intel_display_driver.c

193

rw_init(&display->pps.mutex, "ppsm");

sys/dev/pci/drm/i915/display/intel_display_types.h

1774

struct intel_pps pps;

sys/dev/pci/drm/i915/display/intel_display_types.h

348

struct intel_pps_delays pps;

sys/dev/pci/drm/i915/display/intel_display_types.h

380

struct mipi_pps_data *pps;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

775

struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

859

intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

860

intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

861

intel_dsi->panel_on_delay = pps->panel_on_delay / 10;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

862

intel_dsi->panel_off_delay = pps->panel_off_delay / 10;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

863

intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;

sys/dev/pci/drm/i915/display/intel_lvds.c

158

struct intel_lvds_pps *pps)

sys/dev/pci/drm/i915/display/intel_lvds.c

162

pps->powerdown_on_reset = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_lvds.c

166

pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

167

pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

168

pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

171

pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

172

pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

175

pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);

sys/dev/pci/drm/i915/display/intel_lvds.c

185

pps->delays.power_cycle = val * 1000;

sys/dev/pci/drm/i915/display/intel_lvds.c

188

pps->delays.power_up == 0 &&

sys/dev/pci/drm/i915/display/intel_lvds.c

189

pps->delays.backlight_on == 0 &&

sys/dev/pci/drm/i915/display/intel_lvds.c

190

pps->delays.power_down == 0 &&

sys/dev/pci/drm/i915/display/intel_lvds.c

191

pps->delays.backlight_off == 0) {

sys/dev/pci/drm/i915/display/intel_lvds.c

196

pps->delays.power_up = 40 * 10;

sys/dev/pci/drm/i915/display/intel_lvds.c

197

pps->delays.backlight_on = 200 * 10;

sys/dev/pci/drm/i915/display/intel_lvds.c

199

pps->delays.power_down = 35 * 10;

sys/dev/pci/drm/i915/display/intel_lvds.c

200

pps->delays.backlight_off = 200 * 10;

sys/dev/pci/drm/i915/display/intel_lvds.c

205

pps->delays.power_up, pps->delays.power_down,

sys/dev/pci/drm/i915/display/intel_lvds.c

206

pps->delays.power_cycle, pps->delays.backlight_on,

sys/dev/pci/drm/i915/display/intel_lvds.c

207

pps->delays.backlight_off, pps->divider,

sys/dev/pci/drm/i915/display/intel_lvds.c

208

pps->port, pps->powerdown_on_reset);

sys/dev/pci/drm/i915/display/intel_lvds.c

212

struct intel_lvds_pps *pps)

sys/dev/pci/drm/i915/display/intel_lvds.c

219

if (pps->powerdown_on_reset)

sys/dev/pci/drm/i915/display/intel_lvds.c

224

REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |

sys/dev/pci/drm/i915/display/intel_lvds.c

225

REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) |

sys/dev/pci/drm/i915/display/intel_lvds.c

226

REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on));

sys/dev/pci/drm/i915/display/intel_lvds.c

229

REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) |

sys/dev/pci/drm/i915/display/intel_lvds.c

230

REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off));

sys/dev/pci/drm/i915/display/intel_lvds.c

233

REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |

sys/dev/pci/drm/i915/display/intel_lvds.c

235

DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1));

sys/dev/pci/drm/i915/display/intel_pps.c

1013

intel_dp->pps.last_power_on = jiffies;

sys/dev/pci/drm/i915/display/intel_pps.c

1044

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1053

drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,

sys/dev/pci/drm/i915/display/intel_pps.c

1066

intel_dp->pps.want_panel_vdd = false;

sys/dev/pci/drm/i915/display/intel_pps.c

1072

intel_dp->pps.panel_power_off_time = ktime_get_boottime();

sys/dev/pci/drm/i915/display/intel_pps.c

1079

fetch_and_zero(&intel_dp->pps.vdd_wakeref));

sys/dev/pci/drm/i915/display/intel_pps.c

1139

intel_dp->pps.last_backlight_off = jiffies;

sys/dev/pci/drm/i915/display/intel_pps.c

1173

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1176

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_pps.c

1199

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_pps.c

1207

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1212

drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,

sys/dev/pci/drm/i915/display/intel_pps.c

1217

if (intel_dp->pps.vlv_pps_pipe != pipe)

sys/dev/pci/drm/i915/display/intel_pps.c

1246

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_pps.c

1247

intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1256

intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);

sys/dev/pci/drm/i915/display/intel_pps.c

1271

pipe = intel_dp->pps.vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1287

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1289

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_pps.c

1291

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE &&

sys/dev/pci/drm/i915/display/intel_pps.c

1292

intel_dp->pps.vlv_pps_pipe != crtc->pipe) {

sys/dev/pci/drm/i915/display/intel_pps.c

1307

intel_dp->pps.vlv_active_pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1313

intel_dp->pps.vlv_pps_pipe = crtc->pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

1334

intel_dp->pps.vlv_active_pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_pps.c

1342

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1357

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

sys/dev/pci/drm/i915/display/intel_pps.c

1358

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_pps.c

1383

intel_dp->pps.panel_power_off_time = 0;

sys/dev/pci/drm/i915/display/intel_pps.c

1384

intel_dp->pps.last_power_on = jiffies;

sys/dev/pci/drm/i915/display/intel_pps.c

1385

intel_dp->pps.last_backlight_off = jiffies;

sys/dev/pci/drm/i915/display/intel_pps.c

1443

struct intel_pps_delays *sw = &intel_dp->pps.pps_delays;

sys/dev/pci/drm/i915/display/intel_pps.c

1481

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1483

if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))

sys/dev/pci/drm/i915/display/intel_pps.c

1484

intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);

sys/dev/pci/drm/i915/display/intel_pps.c

1486

*bios = intel_dp->pps.bios_pps_delays;

sys/dev/pci/drm/i915/display/intel_pps.c

1497

*vbt = connector->panel.vbt.edp.pps;

sys/dev/pci/drm/i915/display/intel_pps.c

1523

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1539

*final = &intel_dp->pps.pps_delays;

sys/dev/pci/drm/i915/display/intel_pps.c

1541

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1563

intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up);

sys/dev/pci/drm/i915/display/intel_pps.c

1564

intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on);

sys/dev/pci/drm/i915/display/intel_pps.c

1565

intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off);

sys/dev/pci/drm/i915/display/intel_pps.c

1566

intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down);

sys/dev/pci/drm/i915/display/intel_pps.c

1567

intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle);

sys/dev/pci/drm/i915/display/intel_pps.c

1571

intel_dp->pps.panel_power_up_delay,

sys/dev/pci/drm/i915/display/intel_pps.c

1572

intel_dp->pps.panel_power_down_delay,

sys/dev/pci/drm/i915/display/intel_pps.c

1573

intel_dp->pps.panel_power_cycle_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

1576

intel_dp->pps.backlight_on_delay,

sys/dev/pci/drm/i915/display/intel_pps.c

1577

intel_dp->pps.backlight_off_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

1604

const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays;

sys/dev/pci/drm/i915/display/intel_pps.c

1606

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

1721

intel_dp->pps.initializing = true;

sys/dev/pci/drm/i915/display/intel_pps.c

1722

INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);

sys/dev/pci/drm/i915/display/intel_pps.c

1751

intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,

sys/dev/pci/drm/i915/display/intel_pps.c

1754

intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);

sys/dev/pci/drm/i915/display/intel_pps.c

1757

intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;

sys/dev/pci/drm/i915/display/intel_pps.c

1768

memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));

sys/dev/pci/drm/i915/display/intel_pps.c

1772

intel_dp->pps.initializing = false;

sys/dev/pci/drm/i915/display/intel_pps.c

1800

display->pps.mmio_base = PCH_PPS_BASE;

sys/dev/pci/drm/i915/display/intel_pps.c

1802

display->pps.mmio_base = VLV_PPS_BASE;

sys/dev/pci/drm/i915/display/intel_pps.c

1804

display->pps.mmio_base = PPS_BASE;

sys/dev/pci/drm/i915/display/intel_pps.c

1816

intel_dp->pps.panel_power_up_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

1818

intel_dp->pps.panel_power_down_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

1820

intel_dp->pps.panel_power_cycle_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

1822

intel_dp->pps.backlight_on_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

1824

intel_dp->pps.backlight_off_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

185

intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

sys/dev/pci/drm/i915/display/intel_pps.c

186

intel_dp->pps.vlv_active_pipe !=

sys/dev/pci/drm/i915/display/intel_pps.c

187

intel_dp->pps.vlv_pps_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

189

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_pps.c

190

pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

193

intel_dp->pps.vlv_pps_pipe != INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_pps.c

195

if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_pps.c

196

pipes &= ~(1 << intel_dp->pps.vlv_active_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

213

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

218

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

sys/dev/pci/drm/i915/display/intel_pps.c

219

intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

221

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_pps.c

222

return intel_dp->pps.vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

234

intel_dp->pps.vlv_pps_pipe = pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

251

return intel_dp->pps.vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_pps.c

258

int pps_idx = intel_dp->pps.pps_idx;

sys/dev/pci/drm/i915/display/intel_pps.c

260

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

265

if (!intel_dp->pps.bxt_pps_reset)

sys/dev/pci/drm/i915/display/intel_pps.c

268

intel_dp->pps.bxt_pps_reset = false;

sys/dev/pci/drm/i915/display/intel_pps.c

326

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

330

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

sys/dev/pci/drm/i915/display/intel_pps.c

333

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_pps.c

334

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

sys/dev/pci/drm/i915/display/intel_pps.c

337

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_pps.c

338

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

sys/dev/pci/drm/i915/display/intel_pps.c

342

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) {

sys/dev/pci/drm/i915/display/intel_pps.c

36

struct intel_pps *pps = &intel_dp->pps;

sys/dev/pci/drm/i915/display/intel_pps.c

379

if (intel_dp->pps.pps_idx == 1 &&

sys/dev/pci/drm/i915/display/intel_pps.c

39

switch (pps->vlv_pps_pipe) {

sys/dev/pci/drm/i915/display/intel_pps.c

407

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

416

intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;

sys/dev/pci/drm/i915/display/intel_pps.c

418

intel_dp->pps.pps_idx = 0;

sys/dev/pci/drm/i915/display/intel_pps.c

420

if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))

sys/dev/pci/drm/i915/display/intel_pps.c

421

intel_dp->pps.pps_idx = -1;

sys/dev/pci/drm/i915/display/intel_pps.c

424

if (intel_dp->pps.pps_idx < 0)

sys/dev/pci/drm/i915/display/intel_pps.c

425

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);

sys/dev/pci/drm/i915/display/intel_pps.c

427

if (intel_dp->pps.pps_idx < 0)

sys/dev/pci/drm/i915/display/intel_pps.c

428

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);

sys/dev/pci/drm/i915/display/intel_pps.c

430

if (intel_dp->pps.pps_idx < 0) {

sys/dev/pci/drm/i915/display/intel_pps.c

431

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);

sys/dev/pci/drm/i915/display/intel_pps.c

467

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

sys/dev/pci/drm/i915/display/intel_pps.c

470

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

sys/dev/pci/drm/i915/display/intel_pps.c

487

intel_dp->pps.bxt_pps_reset = true;

sys/dev/pci/drm/i915/display/intel_pps.c

51

MISSING_CASE(pps->vlv_pps_pipe);

sys/dev/pci/drm/i915/display/intel_pps.c

512

pps_idx = intel_dp->pps.pps_idx;

sys/dev/pci/drm/i915/display/intel_pps.c

55

switch (pps->pps_idx) {

sys/dev/pci/drm/i915/display/intel_pps.c

551

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

554

intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_pps.c

564

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

567

intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

sys/dev/pci/drm/i915/display/intel_pps.c

61

MISSING_CASE(pps->pps_idx);

sys/dev/pci/drm/i915/display/intel_pps.c

615

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

680

panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);

sys/dev/pci/drm/i915/display/intel_pps.c

682

remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);

sys/dev/pci/drm/i915/display/intel_pps.c

710

wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,

sys/dev/pci/drm/i915/display/intel_pps.c

711

intel_dp->pps.backlight_on_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

716

wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,

sys/dev/pci/drm/i915/display/intel_pps.c

717

intel_dp->pps.backlight_off_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

729

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

751

bool need_to_disable = !intel_dp->pps.want_panel_vdd;

sys/dev/pci/drm/i915/display/intel_pps.c

756

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

758

cancel_delayed_work(&intel_dp->pps.panel_vdd_work);

sys/dev/pci/drm/i915/display/intel_pps.c

759

intel_dp->pps.want_panel_vdd = true;

sys/dev/pci/drm/i915/display/intel_pps.c

764

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

sys/dev/pci/drm/i915/display/intel_pps.c

765

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

sys/dev/pci/drm/i915/display/intel_pps.c

78

mutex_lock(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

797

drm_msleep(intel_dp->pps.panel_power_up_delay);

sys/dev/pci/drm/i915/display/intel_pps.c

835

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

837

drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);

sys/dev/pci/drm/i915/display/intel_pps.c

864

intel_dp->pps.panel_power_off_time = ktime_get_boottime();

sys/dev/pci/drm/i915/display/intel_pps.c

870

fetch_and_zero(&intel_dp->pps.vdd_wakeref));

sys/dev/pci/drm/i915/display/intel_pps.c

88

mutex_unlock(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

880

cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);

sys/dev/pci/drm/i915/display/intel_pps.c

891

struct intel_pps *pps = container_of(to_delayed_work(__work),

sys/dev/pci/drm/i915/display/intel_pps.c

893

struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);

sys/dev/pci/drm/i915/display/intel_pps.c

897

if (!intel_dp->pps.want_panel_vdd)

sys/dev/pci/drm/i915/display/intel_pps.c

911

if (intel_dp->pps.initializing)

sys/dev/pci/drm/i915/display/intel_pps.c

919

delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);

sys/dev/pci/drm/i915/display/intel_pps.c

921

&intel_dp->pps.panel_vdd_work, delay);

sys/dev/pci/drm/i915/display/intel_pps.c

936

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

938

INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,

sys/dev/pci/drm/i915/display/intel_pps.c

944

intel_dp->pps.want_panel_vdd = false;

sys/dev/pci/drm/i915/display/intel_pps.c

969

lockdep_assert_held(&display->pps.mutex);

sys/dev/pci/drm/i915/display/intel_pps.c

99

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

sys/dev/pci/drm/i915/display/intel_pps_regs.h

17

_MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100)

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1016

struct sdvo_lvds_pps pps[4];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1529

struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177+ */

sys/dev/pci/drm/i915/display/intel_vdsc.c

416

static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,

sys/dev/pci/drm/i915/display/intel_vdsc.c

429

dsc_reg[2] = BMG_DSC2_PPS(pipe, pps);

sys/dev/pci/drm/i915/display/intel_vdsc.c

431

dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);

sys/dev/pci/drm/i915/display/intel_vdsc.c

433

dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);

sys/dev/pci/drm/i915/display/intel_vdsc.c

437

int pps, u32 pps_val)

sys/dev/pci/drm/i915/display/intel_vdsc.c

448

intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);

sys/dev/pci/drm/i915/display/intel_vdsc.c

717

struct drm_dsc_picture_parameter_set pps;

sys/dev/pci/drm/i915/display/intel_vdsc.c

723

drm_dsc_pps_payload_pack(&pps, vdsc_cfg);

sys/dev/pci/drm/i915/display/intel_vdsc.c

728

mipi_dsi_picture_parameter_set(dsi, &pps);

sys/dev/pci/drm/i915/display/intel_vdsc.c

859

static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,

sys/dev/pci/drm/i915/display/intel_vdsc.c

872

intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);

sys/dev/pci/drm/i915/display/intel_vdsc.c

888

static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)

sys/dev/pci/drm/i915/display/intel_vdsc.c

894

val = intel_dsc_pps_read(crtc_state, pps, &all_equal);

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

58

#define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

59

#define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

81

#define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

82

#define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/display/intel_vdsc_regs.h

83

#define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4))

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

917

off_t offset, vaddr_t vaddr, vm_page_t *pps, int npages, int centeridx,

sys/dev/pci/drm/i915/gem/i915_gem_mman.h

42

off_t offset, vaddr_t vaddr, vm_page_t *pps, int npages,

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

1222

vm_fault_ttm(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,

sys/dev/pci/drm/radeon/radeon_gem.c

85

radeon_gem_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,

sys/dev/pci/drm/ttm/ttm_bo_vm.c

591

ttm_bo_vm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,

sys/dev/pci/if_oce.c

3564

struct oce_pport_stats *pps;

sys/dev/pci/if_oce.c

3577

pps = &cmd->params.rsp.pps;

sys/dev/pci/if_oce.c

3579

*rxe = pps->rx_discards + pps->rx_errors + pps->rx_crc_errors +

sys/dev/pci/if_oce.c

3580

pps->rx_alignment_errors + pps->rx_symbol_errors +

sys/dev/pci/if_oce.c

3581

pps->rx_frames_too_long + pps->rx_internal_mac_errors +

sys/dev/pci/if_oce.c

3582

pps->rx_undersize_pkts + pps->rx_oversize_pkts + pps->rx_jabbers +

sys/dev/pci/if_oce.c

3583

pps->rx_control_frames_unknown_opcode + pps->rx_in_range_errors +

sys/dev/pci/if_oce.c

3584

pps->rx_out_of_range_errors + pps->rx_ip_checksum_errors +

sys/dev/pci/if_oce.c

3585

pps->rx_tcp_checksum_errors + pps->rx_udp_checksum_errors +

sys/dev/pci/if_oce.c

3586

pps->rx_fifo_overflow + pps->rx_input_fifo_overflow +

sys/dev/pci/if_oce.c

3587

pps->rx_drops_too_many_frags + pps->rx_drops_mtu;

sys/dev/pci/if_oce.c

3589

*txe = pps->tx_discards + pps->tx_errors + pps->tx_internal_mac_errors;

sys/dev/pci/if_ocereg.h

2408

struct oce_pport_stats pps;

sys/sys/videoio.h

1637

#define V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice) \

sys/sys/videoio.h

1638

((((pps)->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && \

sys/sys/videoio.h

1641

((pps)->weighted_bipred_idc == 1 && \

sys/uvm/uvm_aobj.c

1002

if (pps[lcv] == PGO_DONTCARE)

sys/uvm/uvm_aobj.c

1026

pps[lcv] = ptmp;

sys/uvm/uvm_aobj.c

1048

if (pps[lcv] != NULL ||

sys/uvm/uvm_aobj.c

1071

while (pps[lcv] == NULL) {

sys/uvm/uvm_aobj.c

1117

pps[lcv] = ptmp;

sys/uvm/uvm_aobj.c

1124

if (pps[lcv])

sys/uvm/uvm_aobj.c

1185

pps[lcv] = ptmp;

sys/uvm/uvm_aobj.c

971

uao_get(struct uvm_object *uobj, voff_t offset, struct vm_page **pps,

sys/uvm/uvm_device.c

312

udv_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps, int npages,

sys/uvm/uvm_device.c

363

if (pps[lcv] == PGO_DONTCARE)

sys/uvm/uvm_pager.c

232

uvm_pagermapin(struct vm_page **pps, int npages, int flags)

sys/uvm/uvm_pager.c

245

KASSERT(pps[0]);

sys/uvm/uvm_pager.c

246

KASSERT(pps[0]->pg_flags & PG_BUSY);

sys/uvm/uvm_pager.c

247

return pmap_map_direct(pps[0]);

sys/uvm/uvm_pager.c

263

pp = *pps++;

sys/uvm/uvm_pager.c

332

uvm_mk_pcluster(struct uvm_object *uobj, struct vm_page **pps, int *npages,

sys/uvm/uvm_pager.c

355

pps[0] = center;

sys/uvm/uvm_pager.c

357

return pps;

sys/uvm/uvm_pager.c

362

pps[center_idx] = center; /* plug in the center page */

sys/uvm/uvm_pager.c

363

ppsp = &pps[center_idx];

sys/uvm/uvm_pdaemon.c

571

struct vm_page *pps[SWCLUSTPAGES], **ppsp;

sys/uvm/uvm_pdaemon.c

804

ppsp = pps;

sys/uvm/uvm_pdaemon.c

805

npages = nitems(pps);

sys/uvm/uvm_swap.c

1649

uvm_swap_io(struct vm_page **pps, int startslot, int npages, int flags)

sys/uvm/uvm_swap.c

1678

kva = uvm_pagermapin(pps, npages, mapinflags);

sys/uvm/uvm_swap.c

1721

if (VM_PAGE_TO_PHYS(pps[i]) < dma_constraint.ucr_low ||

sys/uvm/uvm_swap.c

1722

VM_PAGE_TO_PHYS(pps[i]) > dma_constraint.ucr_high) {

sys/uvm/uvm_swap.c

1804

uvm_swap_dropcluster(pps, opages, 0);

sys/uvm/uvm_swap.c

332

uvm_swap_allocpages(struct vm_page **pps, int npages)

sys/uvm/uvm_swap.c

343

pps[i] = TAILQ_FIRST(&pgl);

sys/uvm/uvm_swap.c

345

atomic_setbits_int(&pps[i]->pg_flags, PG_BUSY);

sys/uvm/uvm_swap.c

346

TAILQ_REMOVE(&pgl, pps[i], pageq);

sys/uvm/uvm_swap.c

353

uvm_swap_freepages(struct vm_page **pps, int npages)

sys/uvm/uvm_swap.c

358

uvm_pagefree(pps[i]);

sys/uvm/uvm_vnode.c

1002

if (pps[lcv] != NULL || (lcv != centeridx &&

sys/uvm/uvm_vnode.c

1021

while (pps[lcv] == NULL) { /* top of "pps" while loop */

sys/uvm/uvm_vnode.c

1060

pps[lcv] = ptmp;

sys/uvm/uvm_vnode.c

1068

if (pps[lcv])

sys/uvm/uvm_vnode.c

1108

pps[lcv] = ptmp;

sys/uvm/uvm_vnode.c

1127

uvn_io(struct uvm_vnode *uvn, vm_page_t *pps, int npages, int flags, int rw)

sys/uvm/uvm_vnode.c

1146

file_offset = pps[0]->offset;

sys/uvm/uvm_vnode.c

1167

kva = uvm_pagermapin(pps, npages, mapinflags);

sys/uvm/uvm_vnode.c

1182

kva = uvm_pagermapin(pps, npages,

sys/uvm/uvm_vnode.c

587

struct vm_page *pps[MAXBSIZE >> PAGE_SHIFT], **ppsp;

sys/uvm/uvm_vnode.c

702

ppsp = pps;

sys/uvm/uvm_vnode.c

703

npages = sizeof(pps) / sizeof(struct vm_page *);

sys/uvm/uvm_vnode.c

865

uvn_put(struct uvm_object *uobj, struct vm_page **pps, int npages, int flags)

sys/uvm/uvm_vnode.c

891

retval = uvn_io((struct uvm_vnode*)uobj, pps, npages, flags, UIO_WRITE);

sys/uvm/uvm_vnode.c

909

uvn_get(struct uvm_object *uobj, voff_t offset, struct vm_page **pps,

sys/uvm/uvm_vnode.c

939

if (pps[lcv] == PGO_DONTCARE)

sys/uvm/uvm_vnode.c

964

pps[lcv] = ptmp;

usr.bin/systat/pftop.c

1605

double pps;

usr.bin/systat/pftop.c

1607

pps = (double)(new_pkts - last_pkts) / interval;

usr.bin/systat/pftop.c

1608

return (pps);

usr.bin/systat/pftop.c

1616

double interval, pps, bps;

usr.bin/systat/pftop.c

1663

pps = calc_pps(node->qstats.data.xmit_cnt.packets,

usr.bin/systat/pftop.c

1669

if (pps > 0 && pps < 1)

usr.bin/systat/pftop.c

1670

tbprintf("%-3.1lf", pps);

usr.bin/systat/pftop.c

1672

tbprintf("%u", (unsigned int)pps);

usr.bin/tcpbench/tcpbench.c

528

unsigned long long total_elapsed, since_last, pps;

usr.bin/tcpbench/tcpbench.c

546

pps = (udp_sc->udp_slice_pkts * 1000) / since_last;

usr.bin/tcpbench/tcpbench.c

563

ptb->sflag ? "Rx" : "Tx", pps);

usr.sbin/bpflogd/bpflogd.c

566

struct pcap_pkthdr pps[PCAP_PKTS], *pp;

usr.sbin/bpflogd/bpflogd.c

621

pp = &pps[np++];