sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

176

enum phyd32clk_clock_source phyd32clk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

279

enum phyd32clk_clock_source phyd32clk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

83

static enum phyd32clk_clock_source get_phy_mux_symclk(

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

85

enum phyd32clk_clock_source src)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

173

enum phyd32clk_clock_source phyd32clk);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

182

enum phyd32clk_clock_source phyd32clk);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2201

enum phyd32clk_clock_source phyd32clk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2214

enum phyd32clk_clock_source src)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

384

enum phyd32clk_clock_source phyd32clk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

207

enum phyd32clk_clock_source phyd32clk);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3032

enum phyd32clk_clock_source phyd32clk;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

800

static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

896

static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

917

enum phyd32clk_clock_source *phyd32clk,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

960

enum phyd32clk_clock_source phyd32clk;

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

123

enum phyd32clk_clock_source phyd32clk);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

132

enum phyd32clk_clock_source phyd32clk);