Symbol: pp_smu_status
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
555
static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
566
static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
582
static enum pp_smu_status
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
599
static enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
622
static enum pp_smu_status
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
645
static enum pp_smu_status pp_nv_set_pstate_handshake_support(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
658
static enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
693
static enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
710
static enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
728
static enum pp_smu_status pp_rn_get_dpm_clock_table(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
744
static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
708
enum pp_smu_status status = 0;
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
174
enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
179
enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
185
enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
190
enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
195
enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
198
enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
203
enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
218
enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
224
enum pp_smu_status (*get_maximum_sustainable_clocks)(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
229
enum pp_smu_status (*get_uclk_dpm_states)(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
241
enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
282
enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
285
enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
301
enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
305
enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
308
enum pp_smu_status (*notify_smu_timeout) (struct pp_smu *pp);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2351
enum pp_smu_status status;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
1998
enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
600
enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,