poll_timeout_us
uint32_t poll_timeout_us;
uint32_t poll_timeout_us,
return dm_atomic_write_poll_read_aux(link, write, poll, read, poll_timeout_us, poll_mask_msb);
uint32_t poll_timeout_us,
return dm_atomic_write_poll_read_i2c(link, write, poll, read, poll_timeout_us, poll_mask_msb);
const bool result = atomic_write_poll_read(link, commands, poll_timeout_us, poll_mask_msb);
uint32_t poll_timeout_us,
const bool result = atomic_write_poll_read(link, commands, poll_timeout_us, poll_mask_msb);
uint32_t poll_timeout_us,
commands[1].fused_io.request.timeout_us = poll_timeout_us;
uint32_t poll_timeout_us,
uint32_t poll_timeout_us,
uint32_t poll_timeout_us,
uint32_t poll_timeout_us,
uint32_t poll_timeout_us,
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),
ret = poll_timeout_us(available = header_credits_available(display, dsi_trans),
ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans),
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL),
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status),
ret = poll_timeout_us(val = hsw_read_dcomp(display),
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS),
ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)),
ret = poll_timeout_us(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux),
ret = poll_timeout_us(is_active = intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
poll_timeout_us(is_connected = dig_port->connected(encoder),
ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
ret = poll_timeout_us(is_busy = is_dsb_busy(display, pipe, dsb->id),
ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
ret = poll_timeout_us(read_ret = shim->read_ksv_ready(dig_port, &ksv_ready),
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
ret = poll_timeout_us(ret = hdcp2_detect_msg_availability(dig_port, msg_id,
ret = poll_timeout_us(current_mode = lspcon_get_current_mode(lspcon),
ret = poll_timeout_us(scic = swsci->scic,
ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),
ret = poll_timeout_us(is_enabled = xelpdp_tc_phy_tcss_power_is_enabled(tc),
ret = poll_timeout_us(is_ready = tc_phy_is_ready(tc),
ret = poll_timeout_us(is_moving = pipe_scanline_is_moving(display, pipe),
ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL),
poll_timeout_us((val) = (op)(addr), cond, sleep_us, timeout_us, false)
poll_timeout_us(op, cond, sleep_us, timeout_us, sleep_before)