sys/arch/macppc/dev/if_wi_obio.c

124

CSR_WRITE_2(sc, WI_INT_EN, 0);

sys/arch/macppc/dev/if_wi_obio.c

125

CSR_WRITE_2(sc, WI_EVENT_ACK, 0xffff);

sys/dev/ic/acx.c

1104

CSR_WRITE_2(sc, ACXREG_INTR_ACK, intr_status);

sys/dev/ic/acx.c

1129

CSR_WRITE_2(sc, ACXREG_INTR_MASK, sc->chip_intr_disable);

sys/dev/ic/acx.c

1130

CSR_WRITE_2(sc, ACXREG_EVENT_MASK, 0);

sys/dev/ic/acx.c

1137

CSR_WRITE_2(sc, ACXREG_INTR_MASK, ~sc->chip_intr_enable);

sys/dev/ic/acx.c

1138

CSR_WRITE_2(sc, ACXREG_EVENT_MASK, ACXRV_EVENT_DISABLE);

sys/dev/ic/acx.c

1434

CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg | ACXRV_SOFT_RESET);

sys/dev/ic/acx.c

1436

CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg);

sys/dev/ic/acx.c

1542

CSR_WRITE_2(sc, ACXREG_ECPU_CTRL, ACXRV_ECPU_START);

sys/dev/ic/acx.c

1550

CSR_WRITE_2(sc, ACXREG_INTR_ACK, ACXRV_INTR_FCS_THRESH);

sys/dev/ic/acx.c

2285

CSR_WRITE_2(sc, ACXREG_INTR_TRIG, ACXRV_TRIG_TX_FINI);

sys/dev/ic/acx.c

2613

CSR_WRITE_2(sc, ACXREG_INTR_TRIG, ACXRV_TRIG_CMD_FINI);

sys/dev/ic/acx.c

2628

CSR_WRITE_2(sc, ACXREG_INTR_ACK, ACXRV_INTR_CMD_FINI);

sys/dev/ic/acxvar.h

94

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b))

sys/dev/ic/acxvar.h

96

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b)))

sys/dev/ic/an.c

1068

CSR_WRITE_2(sc, AN_INT_EN, AN_INTRS);

sys/dev/ic/an.c

1234

CSR_WRITE_2(sc, AN_INT_EN, 0);

sys/dev/ic/an.c

185

CSR_WRITE_2(sc, AN_INT_EN, 0);

sys/dev/ic/an.c

186

CSR_WRITE_2(sc, AN_EVENT_ACK, 0xffff);

sys/dev/ic/an.c

360

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);

sys/dev/ic/an.c

370

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);

sys/dev/ic/an.c

382

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);

sys/dev/ic/an.c

392

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);

sys/dev/ic/an.c

400

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);

sys/dev/ic/an.c

412

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);

sys/dev/ic/an.c

441

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);

sys/dev/ic/an.c

493

CSR_WRITE_2(sc, AN_EVENT_ACK, status & (AN_EV_TX | AN_EV_TX_EXC));

sys/dev/ic/an.c

534

CSR_WRITE_2(sc, AN_INT_EN, 0);

sys/dev/ic/an.c

535

CSR_WRITE_2(sc, AN_EVENT_ACK, ~0);

sys/dev/ic/an.c

550

CSR_WRITE_2(sc, AN_EVENT_ACK, status & ~(AN_INTRS));

sys/dev/ic/an.c

583

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY);

sys/dev/ic/an.c

586

CSR_WRITE_2(sc, AN_PARAM0, val);

sys/dev/ic/an.c

587

CSR_WRITE_2(sc, AN_PARAM1, 0);

sys/dev/ic/an.c

588

CSR_WRITE_2(sc, AN_PARAM2, 0);

sys/dev/ic/an.c

589

CSR_WRITE_2(sc, AN_COMMAND, cmd);

sys/dev/ic/an.c

606

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY);

sys/dev/ic/an.c

609

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD);

sys/dev/ic/an.c

659

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_LINKSTAT);

sys/dev/ic/an.c

683

CSR_WRITE_2(sc, AN_COMMAND, AN_CMD_NOOP2);

sys/dev/ic/an.c

689

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD);

sys/dev/ic/an.c

740

CSR_WRITE_2(sc, AN_SEL0, id);

sys/dev/ic/an.c

741

CSR_WRITE_2(sc, AN_OFF0, off);

sys/dev/ic/an.c

825

CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_ALLOC);

sys/dev/ic/an.c

947

CSR_WRITE_2(sc, AN_SW0, AN_MAGIC);

sys/dev/ic/bwi.c

1017

CSR_WRITE_2(sc, data_reg, v);

sys/dev/ic/bwi.c

1030

CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);

sys/dev/ic/bwi.c

1033

CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);

sys/dev/ic/bwi.c

1077

CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);

sys/dev/ic/bwi.c

1152

CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);

sys/dev/ic/bwi.c

1169

CSR_WRITE_2(sc, 0x60e, 0);

sys/dev/ic/bwi.c

1170

CSR_WRITE_2(sc, 0x610, 0x8000);

sys/dev/ic/bwi.c

1171

CSR_WRITE_2(sc, 0x604, 0);

sys/dev/ic/bwi.c

1172

CSR_WRITE_2(sc, 0x606, 0x200);

sys/dev/ic/bwi.c

1196

CSR_WRITE_2(sc, BWI_MAC_POWERUP_DELAY, sc->sc_pwron_delay);

sys/dev/ic/bwi.c

1245

CSR_WRITE_2(sc, 0x612, 0x50); /* Force Pre-TBTT to 80? */

sys/dev/ic/bwi.c

1281

CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);

sys/dev/ic/bwi.c

1516

CSR_WRITE_2(sc, 0x568, 0);

sys/dev/ic/bwi.c

1517

CSR_WRITE_2(sc, 0x7c0, 0);

sys/dev/ic/bwi.c

1518

CSR_WRITE_2(sc, 0x50c, val_50c);

sys/dev/ic/bwi.c

1519

CSR_WRITE_2(sc, 0x508, 0);

sys/dev/ic/bwi.c

1520

CSR_WRITE_2(sc, 0x50a, 0);

sys/dev/ic/bwi.c

1521

CSR_WRITE_2(sc, 0x54c, 0);

sys/dev/ic/bwi.c

1522

CSR_WRITE_2(sc, 0x56a, 0x14);

sys/dev/ic/bwi.c

1523

CSR_WRITE_2(sc, 0x568, 0x826);

sys/dev/ic/bwi.c

1524

CSR_WRITE_2(sc, 0x500, 0);

sys/dev/ic/bwi.c

1525

CSR_WRITE_2(sc, 0x502, 0x30);

sys/dev/ic/bwi.c

2034

CSR_WRITE_2(sc, ofs, val16);

sys/dev/ic/bwi.c

2143

CSR_WRITE_2(sc, BWI_MAC_PRE_TBTT, pre_tbtt);

sys/dev/ic/bwi.c

2384

CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);

sys/dev/ic/bwi.c

2461

CSR_WRITE_2(mac->mac_sc, BWI_MAC_SLOTTIME,

sys/dev/ic/bwi.c

2813

CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);

sys/dev/ic/bwi.c

2814

CSR_WRITE_2(sc, BWI_PHY_DATA, data);

sys/dev/ic/bwi.c

2823

CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);

sys/dev/ic/bwi.c

3116

CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);

sys/dev/ic/bwi.c

3126

CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);

sys/dev/ic/bwi.c

3163

CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);

sys/dev/ic/bwi.c

3210

CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);

sys/dev/ic/bwi.c

3233

CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);

sys/dev/ic/bwi.c

3241

CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);

sys/dev/ic/bwi.c

3395

CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2);

sys/dev/ic/bwi.c

3402

CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2);

sys/dev/ic/bwi.c

3415

CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);

sys/dev/ic/bwi.c

3736

CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);

sys/dev/ic/bwi.c

3737

CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);

sys/dev/ic/bwi.c

3755

CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);

sys/dev/ic/bwi.c

3786

CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);

sys/dev/ic/bwi.c

3790

CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);

sys/dev/ic/bwi.c

3886

CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));

sys/dev/ic/bwi.c

4113

CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));

sys/dev/ic/bwi.c

4115

CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));

sys/dev/ic/bwi.c

4117

CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));

sys/dev/ic/bwi.c

4319

CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);

sys/dev/ic/bwi.c

4357

CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);

sys/dev/ic/bwi.c

4513

CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);

sys/dev/ic/bwi.c

4515

CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);

sys/dev/ic/bwi.c

4522

CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);

sys/dev/ic/bwi.c

4806

CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);

sys/dev/ic/bwi.c

4835

CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);

sys/dev/ic/bwi.c

4883

CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);

sys/dev/ic/bwi.c

4897

CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);

sys/dev/ic/bwi.c

5198

CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);

sys/dev/ic/bwi.c

5212

CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);

sys/dev/ic/bwi.c

5214

CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);

sys/dev/ic/bwi.c

5238

CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);

sys/dev/ic/bwi.c

5246

CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);

sys/dev/ic/bwi.c

5573

CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);

sys/dev/ic/bwi.c

5574

CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);

sys/dev/ic/bwi.c

5575

CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);

sys/dev/ic/bwi.c

6117

CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);

sys/dev/ic/bwi.c

6194

CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);

sys/dev/ic/bwi.c

6495

CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);

sys/dev/ic/bwi.c

6541

CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);

sys/dev/ic/bwi.c

655

CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);

sys/dev/ic/bwi.c

6562

CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);

sys/dev/ic/bwi.c

8314

CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,

sys/dev/ic/bwi.c

8322

CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);

sys/dev/ic/bwivar.h

87

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))

sys/dev/ic/bwivar.h

92

CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

97

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))

sys/dev/ic/fxp.c

1136

CSR_WRITE_2(sc, FXP_CSR_SCB_COMMAND, cmd);

sys/dev/ic/fxp.c

1420

CSR_WRITE_2(sc, FXP_CSR_SCB_COMMAND,

sys/dev/ic/fxp.c

212

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

214

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);

sys/dev/ic/fxp.c

216

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

229

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);

sys/dev/ic/fxp.c

232

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);

sys/dev/ic/fxp.c

237

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);

sys/dev/ic/fxp.c

241

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);

sys/dev/ic/fxp.c

246

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);

sys/dev/ic/fxp.c

253

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);

sys/dev/ic/fxp.c

258

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);

sys/dev/ic/fxp.c

261

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);

sys/dev/ic/fxp.c

556

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);

sys/dev/ic/fxp.c

566

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

567

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,

sys/dev/ic/fxp.c

570

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

578

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);

sys/dev/ic/fxp.c

579

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,

sys/dev/ic/fxp.c

584

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);

sys/dev/ic/fxp.c

587

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);

sys/dev/ic/fxp.c

607

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);

sys/dev/ic/fxp.c

617

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

618

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,

sys/dev/ic/fxp.c

621

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

633

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

634

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,

sys/dev/ic/fxp.c

637

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

646

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,

sys/dev/ic/fxp.c

652

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/fxp.c

656

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);

sys/dev/ic/fxp.c

783

CSR_WRITE_2(sc, FXP_CSR_SCB_STATUS,

sys/dev/ic/fxp.c

797

CSR_WRITE_2(sc, FXP_CSR_SCB_STATUS,

sys/dev/ic/if_wi.c

1237

CSR_WRITE_2(sc, WI_DATA1, ltv->wi_len);

sys/dev/ic/if_wi.c

1238

CSR_WRITE_2(sc, WI_DATA1, ltv->wi_type);

sys/dev/ic/if_wi.c

1271

CSR_WRITE_2(sc, selreg, id);

sys/dev/ic/if_wi.c

1272

CSR_WRITE_2(sc, offreg, off);

sys/dev/ic/if_wi.c

1326

CSR_WRITE_2(sc, WI_DATA0, 0x1234);

sys/dev/ic/if_wi.c

1327

CSR_WRITE_2(sc, WI_DATA0, 0x5678);

sys/dev/ic/if_wi.c

1364

CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_ALLOC);

sys/dev/ic/if_wi.c

1370

CSR_WRITE_2(sc, WI_DATA0, 0);

sys/dev/ic/if_wi.c

444

CSR_WRITE_2(sc, WI_INT_EN, mode);

sys/dev/ic/if_wi.c

451

CSR_WRITE_2(sc, WI_EVENT_ACK, mode);

sys/dev/ic/if_wi.c

466

CSR_WRITE_2(sc, WI_INT_EN, 0);

sys/dev/ic/if_wi.c

467

CSR_WRITE_2(sc, WI_EVENT_ACK, 0xffff);

sys/dev/ic/if_wi.c

472

CSR_WRITE_2(sc, WI_INT_EN, 0);

sys/dev/ic/if_wi.c

475

CSR_WRITE_2(sc, WI_EVENT_ACK, ~WI_INTRS);

sys/dev/ic/if_wi.c

479

CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX);

sys/dev/ic/if_wi.c

484

CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_TX);

sys/dev/ic/if_wi.c

490

CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_ALLOC);

sys/dev/ic/if_wi.c

497

CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_INFO);

sys/dev/ic/if_wi.c

502

CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_TX_EXC);

sys/dev/ic/if_wi.c

506

CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_INFO_DROP);

sys/dev/ic/if_wi.c

510

CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);

sys/dev/ic/if_wi.c

936

CSR_WRITE_2(sc, WI_PARAM0, val0);

sys/dev/ic/if_wi.c

937

CSR_WRITE_2(sc, WI_PARAM1, val1);

sys/dev/ic/if_wi.c

938

CSR_WRITE_2(sc, WI_PARAM2, val2);

sys/dev/ic/if_wi.c

939

CSR_WRITE_2(sc, WI_COMMAND, cmd);

sys/dev/ic/if_wi.c

950

CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD);

sys/dev/ic/mtd8xx.c

284

CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val);

sys/dev/ic/re.c

1547

CSR_WRITE_2(sc, RL_IMR, 0);

sys/dev/ic/re.c

1555

CSR_WRITE_2(sc, RL_ISR, status);

sys/dev/ic/re.c

1608

CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs);

sys/dev/ic/re.c

1915

CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);

sys/dev/ic/re.c

1997

CSR_WRITE_2(sc, RL_ISR, sc->rl_intrs);

sys/dev/ic/re.c

2009

CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);

sys/dev/ic/re.c

2011

CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);

sys/dev/ic/re.c

2178

CSR_WRITE_2(sc, RL_IMR, 0x0000);

sys/dev/ic/re.c

2179

CSR_WRITE_2(sc, RL_ISR, 0xFFFF);

sys/dev/ic/re.c

2242

CSR_WRITE_2(sc, RL_IM,

sys/dev/ic/re.c

2252

CSR_WRITE_2(sc, RL_IM, 0);

sys/dev/ic/re.c

2340

CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs);

sys/dev/ic/re.c

2342

CSR_WRITE_2(sc, RL_IMR, 0);

sys/dev/ic/re.c

534

CSR_WRITE_2(sc, re8139_reg, data);

sys/dev/ic/rtl81x9.c

1079

CSR_WRITE_2(sc, RL_IMR, 0x0000);

sys/dev/ic/rtl81x9.c

1320

CSR_WRITE_2(sc, rl8139_reg, val);

sys/dev/ic/rtl81x9.c

318

CSR_WRITE_2(sc, RL_MII, 0);

sys/dev/ic/rtl81x9.c

664

CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);

sys/dev/ic/rtl81x9.c

754

CSR_WRITE_2(sc, RL_IMR, 0x0000);

sys/dev/ic/rtl81x9.c

762

CSR_WRITE_2(sc, RL_ISR, status);

sys/dev/ic/rtl81x9.c

775

CSR_WRITE_2(sc, RL_IMR, RL_INTRS);

sys/dev/ic/rtl81x9.c

954

CSR_WRITE_2(sc, RL_IMR, RL_INTRS);

sys/dev/ic/rtl81x9reg.h

981

CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))

sys/dev/ic/rtl81x9reg.h

984

CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))

sys/dev/ic/xl.c

1228

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);

sys/dev/ic/xl.c

1230

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);

sys/dev/ic/xl.c

1296

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);

sys/dev/ic/xl.c

1360

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);

sys/dev/ic/xl.c

1394

CSR_WRITE_2(sc, XL_COMMAND,

sys/dev/ic/xl.c

1397

CSR_WRITE_2(sc, XL_COMMAND,

sys/dev/ic/xl.c

1400

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);

sys/dev/ic/xl.c

1401

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);

sys/dev/ic/xl.c

1403

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);

sys/dev/ic/xl.c

1404

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);

sys/dev/ic/xl.c

1429

CSR_WRITE_2(sc, XL_COMMAND,

sys/dev/ic/xl.c

1718

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);

sys/dev/ic/xl.c

1738

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);

sys/dev/ic/xl.c

1869

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);

sys/dev/ic/xl.c

1872

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);

sys/dev/ic/xl.c

1885

CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);

sys/dev/ic/xl.c

1888

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);

sys/dev/ic/xl.c

1890

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);

sys/dev/ic/xl.c

1917

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);

sys/dev/ic/xl.c

1929

CSR_WRITE_2(sc, XL_COMMAND,

sys/dev/ic/xl.c

1946

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);

sys/dev/ic/xl.c

1950

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);

sys/dev/ic/xl.c

1957

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);

sys/dev/ic/xl.c

1962

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);

sys/dev/ic/xl.c

1972

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);

sys/dev/ic/xl.c

1974

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);

sys/dev/ic/xl.c

1984

CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);

sys/dev/ic/xl.c

1993

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);

sys/dev/ic/xl.c

1998

CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);

sys/dev/ic/xl.c

1999

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);

sys/dev/ic/xl.c

2004

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);

sys/dev/ic/xl.c

2005

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);

sys/dev/ic/xl.c

2006

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);

sys/dev/ic/xl.c

2012

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));

sys/dev/ic/xl.c

2016

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);

sys/dev/ic/xl.c

2018

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);

sys/dev/ic/xl.c

2294

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);

sys/dev/ic/xl.c

2295

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);

sys/dev/ic/xl.c

2296

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);

sys/dev/ic/xl.c

2297

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);

sys/dev/ic/xl.c

2299

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);

sys/dev/ic/xl.c

2300

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);

sys/dev/ic/xl.c

2304

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);

sys/dev/ic/xl.c

2306

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);

sys/dev/ic/xl.c

2310

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);

sys/dev/ic/xl.c

2311

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);

sys/dev/ic/xl.c

2312

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);

sys/dev/ic/xl.c

2327

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);

sys/dev/ic/xl.c

242

CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \

sys/dev/ic/xl.c

2424

CSR_WRITE_2(sc, 12, n);

sys/dev/ic/xl.c

246

CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \

sys/dev/ic/xl.c

2593

CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);

sys/dev/ic/xl.c

2646

CSR_WRITE_2(sc, XL_W7_BM_PME, XL_BM_PME_MAGIC);

sys/dev/ic/xl.c

2649

CSR_WRITE_2(sc, XL_W7_BM_PME, 0);

sys/dev/ic/xl.c

316

CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);

sys/dev/ic/xl.c

529

CSR_WRITE_2(sc, XL_W0_EE_CMD,

sys/dev/ic/xl.c

532

CSR_WRITE_2(sc, XL_W0_EE_CMD,

sys/dev/ic/xl.c

589

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT | rxfilt);

sys/dev/ic/xl.c

632

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);

sys/dev/ic/xl.c

639

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH |

sys/dev/ic/xl.c

646

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT | rxfilt);

sys/dev/ic/xl.c

666

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);

sys/dev/ic/xl.c

748

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);

sys/dev/ic/xl.c

750

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);

sys/dev/ic/xl.c

753

CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);

sys/dev/ic/xl.c

764

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |

sys/dev/ic/xl.c

791

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);

sys/dev/ic/xl.c

794

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);

sys/dev/ic/xl.c

800

CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,

sys/dev/ic/xlreg.h

658

CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x)

sys/dev/isa/if_ex.c

350

CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);

sys/dev/isa/if_ex.c

352

CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);

sys/dev/isa/if_ex.c

353

CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);

sys/dev/isa/if_ex.c

425

CSR_WRITE_2(sc, MASK_REG, All_Int);

sys/dev/isa/if_ex.c

446

CSR_WRITE_2(sc, HOST_ADDR_REG, dest);

sys/dev/isa/if_ex.c

447

CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);

sys/dev/isa/if_ex.c

448

CSR_WRITE_2(sc, IO_PORT_REG, 0);

sys/dev/isa/if_ex.c

449

CSR_WRITE_2(sc, IO_PORT_REG, next);

sys/dev/isa/if_ex.c

450

CSR_WRITE_2(sc, IO_PORT_REG, data_len);

sys/dev/isa/if_ex.c

479

CSR_WRITE_2(sc, HOST_ADDR_REG,

sys/dev/isa/if_ex.c

481

CSR_WRITE_2(sc, IO_PORT_REG, dest);

sys/dev/isa/if_ex.c

483

CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_last +

sys/dev/isa/if_ex.c

486

CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_last +

sys/dev/isa/if_ex.c

488

CSR_WRITE_2(sc, IO_PORT_REG, i | Ch_bit);

sys/dev/isa/if_ex.c

499

CSR_WRITE_2(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));

sys/dev/isa/if_ex.c

502

CSR_WRITE_2(sc, XMT_BAR, dest);

sys/dev/isa/if_ex.c

618

CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_head);

sys/dev/isa/if_ex.c

651

CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);

sys/dev/isa/if_ex.c

714

CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);

sys/dev/isa/if_ex.c

718

CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit);

sys/dev/isa/if_ex.c

720

CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_head - 2);

sys/dev/isa/if_ex.c

815

CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_lower_limit);

sys/dev/isa/if_ex.c

816

CSR_WRITE_2(sc, IO_PORT_REG, MC_Setup_CMD);

sys/dev/isa/if_ex.c

817

CSR_WRITE_2(sc, IO_PORT_REG, 0);

sys/dev/isa/if_ex.c

818

CSR_WRITE_2(sc, IO_PORT_REG, 0);

sys/dev/isa/if_ex.c

819

CSR_WRITE_2(sc, IO_PORT_REG, (count + 1) * 6);

sys/dev/isa/if_ex.c

824

CSR_WRITE_2(sc, IO_PORT_REG, *addr++);

sys/dev/isa/if_ex.c

825

CSR_WRITE_2(sc, IO_PORT_REG, *addr++);

sys/dev/isa/if_ex.c

826

CSR_WRITE_2(sc, IO_PORT_REG, *addr++);

sys/dev/isa/if_ex.c

834

CSR_WRITE_2(sc, IO_PORT_REG, *addr++);

sys/dev/isa/if_ex.c

835

CSR_WRITE_2(sc, IO_PORT_REG, *addr++);

sys/dev/isa/if_ex.c

836

CSR_WRITE_2(sc, IO_PORT_REG, *addr++);

sys/dev/isa/if_ex.c

839

CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);

sys/dev/pci/if_age.c

1605

CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));

sys/dev/pci/if_age.c

1616

CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));

sys/dev/pci/if_alc.c

1000

CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, linkcfg);

sys/dev/pci/if_alc.c

1939

CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX,

sys/dev/pci/if_alc.c

2418

CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX,

sys/dev/pci/if_alc.c

753

CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);

sys/dev/pci/if_alc.c

757

CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |

sys/dev/pci/if_alc.c

959

CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |

sys/dev/pci/if_ale.c

1678

CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));

sys/dev/pci/if_ale.c

316

CSR_WRITE_2(sc, ALE_GPHY_CTRL,

sys/dev/pci/if_ale.c

320

CSR_WRITE_2(sc, ALE_GPHY_CTRL,

sys/dev/pci/if_ipwreg.h

314

CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \

sys/dev/pci/if_iwireg.h

492

CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \

sys/dev/pci/if_lge.c

1067

CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);

sys/dev/pci/if_msk.c

1491

CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);

sys/dev/pci/if_msk.c

371

CSR_WRITE_2(sc, reg, x);

sys/dev/pci/if_msk.c

809

CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);

sys/dev/pci/if_msk.c

810

CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET);

sys/dev/pci/if_msk.c

812

CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);

sys/dev/pci/if_msk.c

813

CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR);

sys/dev/pci/if_msk.c

816

CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX |

sys/dev/pci/if_msk.c

828

CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);

sys/dev/pci/if_se.c

1274

CSR_WRITE_2(sc, RxMPSControl, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN +

sys/dev/pci/if_se.c

1281

CSR_WRITE_2(sc, RxMacControl, rxfilt);

sys/dev/pci/if_se.c

478

CSR_WRITE_2(sc, RxMacControl, rxfilt);

sys/dev/pci/if_sk.c

1338

CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);

sys/dev/pci/if_sk.c

229

CSR_WRITE_2(sc, reg, x);

sys/dev/pci/if_sk.c

772

CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);

sys/dev/pci/if_sk.c

773

CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);

sys/dev/pci/if_sk.c

775

CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);

sys/dev/pci/if_sk.c

778

CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);

sys/dev/pci/if_sk.c

780

CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);

sys/dev/pci/if_sk.c

782

CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);

sys/dev/pci/if_ste.c

1063

CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);

sys/dev/pci/if_ste.c

1092

CSR_WRITE_2(sc, STE_MACCTL0, 0);

sys/dev/pci/if_ste.c

1093

CSR_WRITE_2(sc, STE_MACCTL1, 0);

sys/dev/pci/if_ste.c

1101

CSR_WRITE_2(sc, STE_ISR, 0xFFFF);

sys/dev/pci/if_ste.c

1102

CSR_WRITE_2(sc, STE_IMR, STE_INTRS);

sys/dev/pci/if_ste.c

1105

CSR_WRITE_2(sc, STE_MAX_FRAMELEN,

sys/dev/pci/if_ste.c

1132

CSR_WRITE_2(sc, STE_IMR, 0);

sys/dev/pci/if_ste.c

119

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)

sys/dev/pci/if_ste.c

122

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)

sys/dev/pci/if_ste.c

207

CSR_WRITE_2(sc, STE_PHYCTL, 0);

sys/dev/pci/if_ste.c

475

CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));

sys/dev/pci/if_ste.c

536

CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);

sys/dev/pci/if_ste.c

537

CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);

sys/dev/pci/if_ste.c

538

CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);

sys/dev/pci/if_ste.c

539

CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);

sys/dev/pci/if_ste.c

590

CSR_WRITE_2(sc, STE_IMR, STE_INTRS);

sys/dev/pci/if_ste.c

721

CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);

sys/dev/pci/if_ste.c

722

CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,

sys/dev/pci/if_ste.c

726

CSR_WRITE_2(sc, STE_TX_STATUS, txstat);

sys/dev/pci/if_stge.c

1140

CSR_WRITE_2(sc, STGE_StationAddress0,

sys/dev/pci/if_stge.c

1142

CSR_WRITE_2(sc, STGE_StationAddress1,

sys/dev/pci/if_stge.c

1144

CSR_WRITE_2(sc, STGE_StationAddress2,

sys/dev/pci/if_stge.c

1188

CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);

sys/dev/pci/if_stge.c

1195

CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);

sys/dev/pci/if_stge.c

1216

CSR_WRITE_2(sc, STGE_IntStatus, 0xffff);

sys/dev/pci/if_stge.c

1217

CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);

sys/dev/pci/if_stge.c

1231

CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);

sys/dev/pci/if_stge.c

1232

CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);

sys/dev/pci/if_stge.c

1238

CSR_WRITE_2(sc, STGE_MaxFrameSize, STGE_JUMBO_FRAMELEN);

sys/dev/pci/if_stge.c

1240

CSR_WRITE_2(sc, STGE_MaxFrameSize, ETHER_MAX_LEN);

sys/dev/pci/if_stge.c

1260

CSR_WRITE_2(sc, STGE_DebugCtrl,

sys/dev/pci/if_stge.c

1264

CSR_WRITE_2(sc, STGE_DebugCtrl,

sys/dev/pci/if_stge.c

1268

CSR_WRITE_2(sc, STGE_DebugCtrl,

sys/dev/pci/if_stge.c

1346

CSR_WRITE_2(sc, STGE_IntEnable, 0);

sys/dev/pci/if_stge.c

1405

CSR_WRITE_2(sc, STGE_EepromCtrl,

sys/dev/pci/if_stge.c

1517

CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode);

sys/dev/pci/if_stge.c

779

CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);

sys/dev/pci/if_tl.c

1246

CSR_WRITE_2(sc, TL_HOST_INT, ints);

sys/dev/pci/if_tl.c

1319

CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);

sys/dev/pci/if_tl.c

294

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

301

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

308

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

315

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

322

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

323

CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);

sys/dev/pci/if_tl.c

329

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

338

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

349

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

360

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

363

CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);

sys/dev/pci/if_tl.c

371

CSR_WRITE_2(sc, TL_DIO_ADDR, reg);

sys/dev/pci/if_tl.c

374

CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);

sys/dev/pci/if_vge.c

1147

CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);

sys/dev/pci/if_vge.c

1465

CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);

sys/dev/pci/if_vge.c

1550

CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);

sys/dev/pci/if_vge.c

1554

CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);

sys/dev/pci/if_vge.c

1555

CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);

sys/dev/pci/if_vge.c

1562

CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);

sys/dev/pci/if_vge.c

1571

CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF);

sys/dev/pci/if_vge.c

1594

CSR_WRITE_2(sc, VGE_SSTIMER, 400);

sys/dev/pci/if_vge.c

1812

CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);

sys/dev/pci/if_vge.c

352

CSR_WRITE_2(sc, VGE_MIIDATA, data);

sys/dev/pci/if_vgevar.h

116

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))

sys/dev/pci/if_vgevar.h

123

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))

sys/dev/pci/if_vr.c

1098

CSR_WRITE_2(sc, VR_ISR, status);

sys/dev/pci/if_vr.c

1454

CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|

sys/dev/pci/if_vr.c

1464

CSR_WRITE_2(sc, VR_ISR, 0xFFFF);

sys/dev/pci/if_vr.c

1465

CSR_WRITE_2(sc, VR_IMR, VR_INTRS);

sys/dev/pci/if_vr.c

1617

CSR_WRITE_2(sc, VR_IMR, 0x0000);

sys/dev/pci/if_vr.c

186

CSR_WRITE_2(sc, reg, \

sys/dev/pci/if_vr.c

190

CSR_WRITE_2(sc, reg, \

sys/dev/pci/if_vr.c

256

CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);

sys/dev/pci/if_vte.c

1059

CSR_WRITE_2(sc, VTE_MRDCR, prog |

sys/dev/pci/if_vte.c

1088

CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);

sys/dev/pci/if_vte.c

1102

CSR_WRITE_2(sc, VTE_MACSM, 0x0002);

sys/dev/pci/if_vte.c

1103

CSR_WRITE_2(sc, VTE_MACSM, 0);

sys/dev/pci/if_vte.c

1112

CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);

sys/dev/pci/if_vte.c

1154

CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);

sys/dev/pci/if_vte.c

1155

CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);

sys/dev/pci/if_vte.c

1156

CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);

sys/dev/pci/if_vte.c

1160

CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);

sys/dev/pci/if_vte.c

1161

CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);

sys/dev/pci/if_vte.c

1164

CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);

sys/dev/pci/if_vte.c

1165

CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);

sys/dev/pci/if_vte.c

1172

CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |

sys/dev/pci/if_vte.c

1185

CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);

sys/dev/pci/if_vte.c

1188

CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |

sys/dev/pci/if_vte.c

119

CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |

sys/dev/pci/if_vte.c

1199

CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);

sys/dev/pci/if_vte.c

1206

CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |

sys/dev/pci/if_vte.c

1213

CSR_WRITE_2(sc, VTE_MRICR, 0);

sys/dev/pci/if_vte.c

1214

CSR_WRITE_2(sc, VTE_MTICR, 0);

sys/dev/pci/if_vte.c

1217

CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);

sys/dev/pci/if_vte.c

1222

CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);

sys/dev/pci/if_vte.c

1223

CSR_WRITE_2(sc, VTE_MISR, 0);

sys/dev/pci/if_vte.c

1255

CSR_WRITE_2(sc, VTE_MIER, 0);

sys/dev/pci/if_vte.c

1256

CSR_WRITE_2(sc, VTE_MECIER, 0);

sys/dev/pci/if_vte.c

1302

CSR_WRITE_2(sc, VTE_MCR0, mcr);

sys/dev/pci/if_vte.c

1326

CSR_WRITE_2(sc, VTE_MCR0, mcr);

sys/dev/pci/if_vte.c

142

CSR_WRITE_2(sc, VTE_MMWD, val);

sys/dev/pci/if_vte.c

143

CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |

sys/dev/pci/if_vte.c

1481

CSR_WRITE_2(sc, VTE_MAR0, mchash[0]);

sys/dev/pci/if_vte.c

1482

CSR_WRITE_2(sc, VTE_MAR1, mchash[1]);

sys/dev/pci/if_vte.c

1483

CSR_WRITE_2(sc, VTE_MAR2, mchash[2]);

sys/dev/pci/if_vte.c

1484

CSR_WRITE_2(sc, VTE_MAR3, mchash[3]);

sys/dev/pci/if_vte.c

1487

CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,

sys/dev/pci/if_vte.c

1489

CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,

sys/dev/pci/if_vte.c

1491

CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,

sys/dev/pci/if_vte.c

1494

CSR_WRITE_2(sc, VTE_MCR0, mcr);

sys/dev/pci/if_vte.c

197

CSR_WRITE_2(sc, VTE_MRICR, val);

sys/dev/pci/if_vte.c

206

CSR_WRITE_2(sc, VTE_MTICR, val);

sys/dev/pci/if_vte.c

695

CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);

sys/dev/pci/if_vte.c

783

CSR_WRITE_2(sc, VTE_MCR0, mcr);

sys/dev/pci/if_vte.c

857

CSR_WRITE_2(sc, VTE_MIER, 0);

sys/dev/pci/if_vte.c

878

CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);

sys/dev/pci/if_wi_pci.c

409

CSR_WRITE_2(sc, WI_SW0, WI_DRVR_MAGIC);

sys/dev/pci/if_wi_pci.c

526

CSR_WRITE_2(sc, WI_INT_EN, 0);

sys/dev/pci/if_wi_pci.c

527

CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);

sys/dev/pcmcia/if_wi_pcmcia.c

411

CSR_WRITE_2(sc, WI_INT_EN, 0);

sys/dev/pcmcia/if_wi_pcmcia.c

412

CSR_WRITE_2(sc, WI_EVENT_ACK, 0xffff);