sys/dev/ic/re.c

1054

CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);

sys/dev/ic/re.c

1056

CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);

sys/dev/ic/re.c

1810

CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);

sys/dev/ic/re.c

1923

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);

sys/dev/ic/re.c

1938

CSR_WRITE_1(sc, RL_LEDSEL, RL_LED_LINK | RL_LED_ACT << 4);

sys/dev/ic/re.c

1943

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/ic/re.c

1976

CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);

sys/dev/ic/re.c

1988

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);

sys/dev/ic/re.c

2014

CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |

sys/dev/ic/re.c

212

CSR_WRITE_1(sc, RL_EECMD, \

sys/dev/ic/re.c

216

CSR_WRITE_1(sc, RL_EECMD, \

sys/dev/ic/re.c

2160

CSR_WRITE_1(sc, RL_COMMAND, 0x00);

sys/dev/ic/re.c

2162

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |

sys/dev/ic/re.c

2176

CSR_WRITE_1(sc, RL_COMMAND, 0x00);

sys/dev/ic/re.c

2314

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);

sys/dev/ic/re.c

2315

CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) |

sys/dev/ic/re.c

2322

CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |

sys/dev/ic/re.c

2326

CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |

sys/dev/ic/re.c

2331

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/ic/re.c

2388

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);

sys/dev/ic/re.c

2395

CSR_WRITE_1(sc, sc->rl_cfg5, val);

sys/dev/ic/re.c

2400

CSR_WRITE_1(sc, sc->rl_cfg3, val);

sys/dev/ic/re.c

2405

CSR_WRITE_1(sc, sc->rl_cfg5, val);

sys/dev/ic/re.c

2409

CSR_WRITE_1(sc, sc->rl_cfg3, val);

sys/dev/ic/re.c

2412

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/ic/re.c

642

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);

sys/dev/ic/re.c

653

CSR_WRITE_1(sc, RL_LDPS, 1);

sys/dev/ic/rtl81x9.c

1078

CSR_WRITE_1(sc, RL_COMMAND, 0x00);

sys/dev/ic/rtl81x9.c

154

CSR_WRITE_1(sc, RL_EECMD, \

sys/dev/ic/rtl81x9.c

158

CSR_WRITE_1(sc, RL_EECMD, \

sys/dev/ic/rtl81x9.c

199

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);

sys/dev/ic/rtl81x9.c

206

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);

sys/dev/ic/rtl81x9.c

221

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/ic/rtl81x9.c

253

CSR_WRITE_1(sc, RL_MII, \

sys/dev/ic/rtl81x9.c

257

CSR_WRITE_1(sc, RL_MII, \

sys/dev/ic/rtl81x9.c

495

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);

sys/dev/ic/rtl81x9.c

922

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);

sys/dev/ic/rtl81x9.c

927

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/ic/rtl81x9.c

938

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);

sys/dev/ic/rtl81x9.c

963

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);

sys/dev/ic/rtl81x9.c

967

CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);

sys/dev/ic/rtl81x9reg.h

975

CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))

sys/dev/ic/rtl81x9reg.h

978

CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))

sys/dev/ic/xl.c

1371

CSR_WRITE_1(sc, XL_DOWN_POLL, 64);

sys/dev/ic/xl.c

1384

CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);

sys/dev/ic/xl.c

1410

CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);

sys/dev/ic/xl.c

1879

CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,

sys/dev/ic/xl.c

1914

CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);

sys/dev/ic/xl.c

1955

CSR_WRITE_1(sc, XL_DOWN_POLL, 64);

sys/dev/ic/xl.c

1989

CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);

sys/dev/ic/xl.c

474

CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);

sys/dev/ic/xl.c

476

CSR_WRITE_1(sc, XL_W3_MAC_CTRL,

sys/dev/ic/xl.c

740

CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);

sys/dev/ic/xl.c

743

CSR_WRITE_1(sc, XL_W3_MAC_CTRL,

sys/dev/isa/if_ex.c

196

CSR_WRITE_1(sc, CMD_REG, Reset_CMD);

sys/dev/isa/if_ex.c

301

CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);

sys/dev/isa/if_ex.c

304

CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);

sys/dev/isa/if_ex.c

306

CSR_WRITE_1(sc, I_ADDR_REG0 + i, sc->arpcom.ac_enaddr[i]);

sys/dev/isa/if_ex.c

314

CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md |

sys/dev/isa/if_ex.c

316

CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins |

sys/dev/isa/if_ex.c

318

CSR_WRITE_1(sc, REG3, (CSR_READ_1(sc, REG3) & 0x3f));

sys/dev/isa/if_ex.c

319

CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);

sys/dev/isa/if_ex.c

320

CSR_WRITE_1(sc, INT_NO_REG, (CSR_READ_1(sc, INT_NO_REG) & 0xf8) |

sys/dev/isa/if_ex.c

334

CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8);

sys/dev/isa/if_ex.c

335

CSR_WRITE_1(sc, RCV_UPPER_LIMIT_REG, sc->rx_upper_limit >> 8);

sys/dev/isa/if_ex.c

336

CSR_WRITE_1(sc, XMT_LOWER_LIMIT_REG, sc->tx_lower_limit >> 8);

sys/dev/isa/if_ex.c

337

CSR_WRITE_1(sc, XMT_UPPER_LIMIT_REG, sc->tx_upper_limit >> 8);

sys/dev/isa/if_ex.c

342

CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT);

sys/dev/isa/if_ex.c

343

CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);

sys/dev/isa/if_ex.c

344

CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));

sys/dev/isa/if_ex.c

345

CSR_WRITE_1(sc, STATUS_REG, All_Int);

sys/dev/isa/if_ex.c

365

CSR_WRITE_1(sc, CMD_REG, Sel_Reset_CMD);

sys/dev/isa/if_ex.c

367

CSR_WRITE_1(sc, CMD_REG, Rcv_Enable_CMD);

sys/dev/isa/if_ex.c

503

CSR_WRITE_1(sc, CMD_REG, Transmit_CMD);

sys/dev/isa/if_ex.c

507

CSR_WRITE_1(sc, CMD_REG, Resume_XMT_List_CMD);

sys/dev/isa/if_ex.c

541

CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);

sys/dev/isa/if_ex.c

542

CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT);

sys/dev/isa/if_ex.c

543

CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);

sys/dev/isa/if_ex.c

544

CSR_WRITE_1(sc, CMD_REG, Rcv_Stop);

sys/dev/isa/if_ex.c

549

CSR_WRITE_1(sc, MASK_REG, All_Int);

sys/dev/isa/if_ex.c

550

CSR_WRITE_1(sc, STATUS_REG, All_Int);

sys/dev/isa/if_ex.c

551

CSR_WRITE_1(sc, CMD_REG, Reset_CMD);

sys/dev/isa/if_ex.c

577

CSR_WRITE_1(sc, STATUS_REG, Rx_Int);

sys/dev/isa/if_ex.c

581

CSR_WRITE_1(sc, STATUS_REG, Tx_Int);

sys/dev/isa/if_ex.c

800

CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);

sys/dev/isa/if_ex.c

801

CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode);

sys/dev/isa/if_ex.c

802

CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));

sys/dev/isa/if_ex.c

803

CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);

sys/dev/isa/if_ex.c

807

CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);

sys/dev/isa/if_ex.c

808

CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Multi_IA);

sys/dev/isa/if_ex.c

809

CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));

sys/dev/isa/if_ex.c

810

CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);

sys/dev/isa/if_ex.c

840

CSR_WRITE_1(sc, CMD_REG, MC_Setup_CMD);

sys/dev/isa/if_ex.c

851

CSR_WRITE_1(sc, STATUS_REG, Exec_Int);

sys/dev/isa/if_ex.c

858

CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);

sys/dev/isa/if_ex.c

859

CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) & 0xDE);

sys/dev/isa/if_ex.c

861

CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));

sys/dev/isa/if_ex.c

862

CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);

sys/dev/isa/if_ex.c

904

CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);

sys/dev/isa/if_ex.c

906

CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);

sys/dev/isa/if_ex.c

947

CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);

sys/dev/isa/if_ex.c

948

CSR_WRITE_1(sc, EEPROM_REG, EECS);

sys/dev/isa/if_ex.c

952

CSR_WRITE_1(sc, EEPROM_REG, outval);

sys/dev/isa/if_ex.c

953

CSR_WRITE_1(sc, EEPROM_REG, outval | EESK);

sys/dev/isa/if_ex.c

955

CSR_WRITE_1(sc, EEPROM_REG, outval);

sys/dev/isa/if_ex.c

958

CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);

sys/dev/isa/if_ex.c

960

CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);

sys/dev/isa/if_ex.c

963

CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);

sys/dev/isa/if_ex.c

967

CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);

sys/dev/isa/if_ex.c

969

CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);

sys/dev/isa/if_ex.c

971

CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);

sys/dev/pci/if_ale.c

1353

CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,

sys/dev/pci/if_ale.c

1639

CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);

sys/dev/pci/if_ale.c

1640

CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);

sys/dev/pci/if_ipw.c

2054

CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap);

sys/dev/pci/if_ipwreg.h

309

CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \

sys/dev/pci/if_iwireg.h

487

CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \

sys/dev/pci/if_msk.c

377

CSR_WRITE_1(sc, reg, x);

sys/dev/pci/if_msk.c

756

CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);

sys/dev/pci/if_msk.c

757

CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);

sys/dev/pci/if_msk.c

760

CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);

sys/dev/pci/if_msk.c

762

CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);

sys/dev/pci/if_msk.c

827

CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);

sys/dev/pci/if_msk.c

834

CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP);

sys/dev/pci/if_msk.c

835

CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR);

sys/dev/pci/if_msk.c

841

CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP);

sys/dev/pci/if_msk.c

842

CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR);

sys/dev/pci/if_re_pci.c

192

CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);

sys/dev/pci/if_re_pci.c

196

CSR_WRITE_1(sc, RL_CFG2, cfg);

sys/dev/pci/if_re_pci.c

200

CSR_WRITE_1(sc, RL_CFG2, cfg);

sys/dev/pci/if_re_pci.c

203

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);

sys/dev/pci/if_se.c

1278

CSR_WRITE_1(sc, RxMacAddr + i, sc->sc_ac.ac_enaddr[i]);

sys/dev/pci/if_sk.c

235

CSR_WRITE_1(sc, reg, x);

sys/dev/pci/if_ste.c

1041

CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);

sys/dev/pci/if_ste.c

1054

CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);

sys/dev/pci/if_ste.c

1060

CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, ETHER_MAX_DIX_LEN >> 8);

sys/dev/pci/if_ste.c

1066

CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (ETHER_MAX_DIX_LEN >> 4));

sys/dev/pci/if_ste.c

1080

CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);

sys/dev/pci/if_ste.c

125

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)

sys/dev/pci/if_ste.c

128

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)

sys/dev/pci/if_ste.c

1346

CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);

sys/dev/pci/if_ste.c

540

CSR_WRITE_1(sc, STE_RX_MODE, rxmode);

sys/dev/pci/if_stge.c

1148

CSR_WRITE_1(sc, STGE_StationAddress0 + i,

sys/dev/pci/if_stge.c

1182

CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);

sys/dev/pci/if_stge.c

1185

CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64);

sys/dev/pci/if_stge.c

1191

CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);

sys/dev/pci/if_stge.c

1192

CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);

sys/dev/pci/if_stge.c

1198

CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);

sys/dev/pci/if_stge.c

1199

CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);

sys/dev/pci/if_stge.c

1592

CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl);

sys/dev/pci/if_tl.c

316

CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);

sys/dev/pci/if_tl.c

341

CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);

sys/dev/pci/if_tl.c

352

CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);

sys/dev/pci/if_vge.c

1201

CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);

sys/dev/pci/if_vge.c

1253

CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);

sys/dev/pci/if_vge.c

1278

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);

sys/dev/pci/if_vge.c

1279

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);

sys/dev/pci/if_vge.c

1297

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);

sys/dev/pci/if_vge.c

1478

CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);

sys/dev/pci/if_vge.c

1515

CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]);

sys/dev/pci/if_vge.c

1558

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);

sys/dev/pci/if_vge.c

1559

CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);

sys/dev/pci/if_vge.c

1565

CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_GIANT);

sys/dev/pci/if_vge.c

1578

CSR_WRITE_1(sc, VGE_CRC2, 0xFF);

sys/dev/pci/if_vge.c

1579

CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B);

sys/dev/pci/if_vge.c

1584

CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);

sys/dev/pci/if_vge.c

1585

CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);

sys/dev/pci/if_vge.c

1586

CSR_WRITE_1(sc, VGE_CRS0,

sys/dev/pci/if_vge.c

1605

CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);

sys/dev/pci/if_vge.c

1609

CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */

sys/dev/pci/if_vge.c

1612

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);

sys/dev/pci/if_vge.c

1613

CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);

sys/dev/pci/if_vge.c

1618

CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */

sys/dev/pci/if_vge.c

1630

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);

sys/dev/pci/if_vge.c

1718

CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE |

sys/dev/pci/if_vge.c

1721

CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_TXFLOWCTL_ENABLE);

sys/dev/pci/if_vge.c

1723

CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_RXFLOWCTL_ENABLE);

sys/dev/pci/if_vge.c

1809

CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);

sys/dev/pci/if_vge.c

1810

CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);

sys/dev/pci/if_vge.c

1813

CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);

sys/dev/pci/if_vge.c

191

CSR_WRITE_1(sc, VGE_EEADDR, addr);

sys/dev/pci/if_vge.c

249

CSR_WRITE_1(sc, VGE_MIICMD, 0);

sys/dev/pci/if_vge.c

268

CSR_WRITE_1(sc, VGE_MIICMD, 0);

sys/dev/pci/if_vge.c

269

CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);

sys/dev/pci/if_vge.c

284

CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);

sys/dev/pci/if_vge.c

313

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/pci/if_vge.c

349

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/pci/if_vge.c

385

CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);

sys/dev/pci/if_vge.c

387

CSR_WRITE_1(sc, VGE_CAM0 + i, 0);

sys/dev/pci/if_vge.c

391

CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);

sys/dev/pci/if_vge.c

393

CSR_WRITE_1(sc, VGE_CAM0 + i, 0);

sys/dev/pci/if_vge.c

395

CSR_WRITE_1(sc, VGE_CAMADDR, 0);

sys/dev/pci/if_vge.c

415

CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);

sys/dev/pci/if_vge.c

419

CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);

sys/dev/pci/if_vge.c

449

CSR_WRITE_1(sc, VGE_CAMADDR, 0);

sys/dev/pci/if_vge.c

516

CSR_WRITE_1(sc, VGE_RXCTL, rxctl);

sys/dev/pci/if_vge.c

524

CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);

sys/dev/pci/if_vge.c

534

CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);

sys/dev/pci/if_vgevar.h

114

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/pci/if_vgevar.h

121

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/pci/if_vr.c

1398

CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);

sys/dev/pci/if_vr.c

1666

CSR_WRITE_1(sc, VR_WOLCRCLR, 0xFF);

sys/dev/pci/if_vr.c

1669

CSR_WRITE_1(sc, VR_PWRCSRCLR, 0xFF);

sys/dev/pci/if_vr.c

178

CSR_WRITE_1(sc, reg, \

sys/dev/pci/if_vr.c

182

CSR_WRITE_1(sc, reg, \

sys/dev/pci/if_vr.c

202

CSR_WRITE_1(sc, VR_MIICMD, \

sys/dev/pci/if_vr.c

206

CSR_WRITE_1(sc, VR_MIICMD, \

sys/dev/pci/if_vr.c

220

CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|

sys/dev/pci/if_vr.c

224

CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);

sys/dev/pci/if_vr.c

251

CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|

sys/dev/pci/if_vr.c

255

CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);

sys/dev/pci/if_vr.c

375

CSR_WRITE_1(sc, VR_RXCFG, rxfilt);

sys/dev/pci/if_wb.c

1374

CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);