sys/arch/amd64/amd64/powernow-k8.c

116

unsigned int pll;

sys/arch/amd64/amd64/powernow-k8.c

133

uint8_t pll;

sys/arch/amd64/amd64/powernow-k8.c

247

WRITE_FIDVID(val, cvid, (uint64_t)cstate->pll * 1000 / 5);

sys/arch/amd64/amd64/powernow-k8.c

257

WRITE_FIDVID(fid, cvid, (uint64_t) cstate->pll * 1000 / 5);

sys/arch/amd64/amd64/powernow-k8.c

378

nstate->pll = PN8_ACPI_CTRL_TO_PLL(ctrl);

sys/arch/amd64/amd64/powernow-k8.c

408

cstate->pll = PN8_ACPI_CTRL_TO_PLL(ctrl);

sys/arch/amd64/amd64/powernow-k8.c

443

cstate->pll = pst->pll;

sys/arch/armv7/exynos/exclock.c

335

exclock_decode_pll_clk(enum clocks pll, unsigned int r, unsigned int k)

sys/arch/armv7/exynos/exclock.c

347

switch (pll)

sys/arch/armv7/exynos/exclock.c

368

if (pll == EPLL) {

sys/arch/armv7/exynos/exclock.c

372

} else if (pll == VPLL) {

sys/arch/armv7/exynos/exclock.c

385

exclock_get_pll_clk(struct exclock_softc *sc, enum clocks pll)

sys/arch/armv7/exynos/exclock.c

389

switch (pll) {

sys/arch/armv7/exynos/exclock.c

391

freq = exclock_decode_pll_clk(pll,

sys/arch/armv7/exynos/exclock.c

395

freq = exclock_decode_pll_clk(pll,

sys/arch/armv7/exynos/exclock.c

399

freq = exclock_decode_pll_clk(pll,

sys/arch/armv7/exynos/exclock.c

403

freq = exclock_decode_pll_clk(pll,

sys/arch/armv7/exynos/exclock.c

408

freq = exclock_decode_pll_clk(pll,

sys/arch/armv7/exynos/exclock.c

413

freq = exclock_decode_pll_clk(pll,

sys/arch/armv7/exynos/exclock.c

424

if (pll == MPLL || pll == BPLL) {

sys/arch/armv7/exynos/exclock.c

428

switch (pll) {

sys/arch/i386/i386/powernow-k8.c

116

unsigned int pll;

sys/arch/i386/i386/powernow-k8.c

133

uint8_t pll;

sys/arch/i386/i386/powernow-k8.c

249

WRITE_FIDVID(val, cvid, (uint64_t)cstate->pll * 1000 / 5);

sys/arch/i386/i386/powernow-k8.c

259

WRITE_FIDVID(fid, cvid, (uint64_t) cstate->pll * 1000 / 5);

sys/arch/i386/i386/powernow-k8.c

345

cstate->pll = pst->pll;

sys/arch/i386/i386/powernow-k8.c

414

cstate->pll = PN8_ACPI_CTRL_TO_PLL(ctrl);

sys/arch/i386/i386/powernow-k8.c

438

cstate->pll = PN8_ACPI_CTRL_TO_PLL(ctrl);

sys/dev/fdt/imxanatop.c

260

imxanatop_decode_pll(enum imxanatop_clocks pll, uint32_t freq)

sys/dev/fdt/imxanatop.c

267

switch (pll) {

sys/dev/fdt/rkclock.c

1448

uint32_t reg, mux, pll, div_con;

sys/dev/fdt/rkclock.c

1458

pll = RK3308_PLL_VPLL1;

sys/dev/fdt/rkclock.c

1460

pll = RK3308_PLL_VPLL0;

sys/dev/fdt/rkclock.c

1463

return rk3308_get_frequency(sc, &pll) / (div_con + 1);

sys/dev/ic/athn.c

755

uint32_t pll;

sys/dev/ic/athn.c

760

pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);

sys/dev/ic/athn.c

761

pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);

sys/dev/ic/athn.c

763

pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);

sys/dev/ic/athn.c

766

pll = 0x142c;

sys/dev/ic/athn.c

768

pll = 0x2850;

sys/dev/ic/athn.c

770

pll |= SM(AR_RTC_9160_PLL_DIV, 0x28);

sys/dev/ic/athn.c

772

pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);

sys/dev/ic/athn.c

774

pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);

sys/dev/ic/athn.c

776

pll |= SM(AR_RTC_9160_PLL_DIV, 0x50);

sys/dev/ic/athn.c

778

pll |= SM(AR_RTC_9160_PLL_DIV, 0x58);

sys/dev/ic/athn.c

780

pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;

sys/dev/ic/athn.c

782

pll |= SM(AR_RTC_PLL_DIV, 0x0a);

sys/dev/ic/athn.c

784

pll |= SM(AR_RTC_PLL_DIV, 0x0b);

sys/dev/ic/athn.c

786

DPRINTFN(5, ("AR_RTC_PLL_CONTROL=0x%08x\n", pll));

sys/dev/ic/athn.c

787

AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll);

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

123

struct amdgpu_pll *pll,

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

131

unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

141

fb_div_min = pll->min_feedback_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

142

fb_div_max = pll->max_feedback_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

144

if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

150

if (pll->flags & AMDGPU_PLL_USE_REF_DIV)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

151

ref_div_min = pll->reference_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

153

ref_div_min = pll->min_ref_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

155

if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

156

pll->flags & AMDGPU_PLL_USE_REF_DIV)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

157

ref_div_max = pll->reference_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

159

ref_div_max = pll->max_ref_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

162

if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

163

post_div_min = pll->post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

164

post_div_max = pll->post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

168

if (pll->flags & AMDGPU_PLL_IS_LCD) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

169

vco_min = pll->lcd_pll_out_min;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

170

vco_max = pll->lcd_pll_out_max;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

172

vco_min = pll->pll_out_min;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

173

vco_max = pll->pll_out_max;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

176

if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

184

if (post_div_min < pll->min_post_div)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

185

post_div_min = pll->min_post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

190

if (post_div_max > pll->max_post_div)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

191

post_div_max = pll->max_post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

196

den = pll->reference_freq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

202

if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

212

diff = abs(target_clock - (pll->reference_freq * fb_div) /

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

216

!(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

233

if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

243

if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

251

*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

252

(pll->reference_freq * *frac_fb_div_p)) /

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.h

28

struct amdgpu_pll *pll,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

826

struct amdgpu_pll *pll;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

836

pll = &adev->clock.ppll[0];

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

839

pll = &adev->clock.ppll[1];

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

844

pll = &adev->clock.ppll[2];

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

849

pll->flags = amdgpu_crtc->pll_flags;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

850

pll->reference_div = amdgpu_crtc->pll_reference_div;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

851

pll->post_div = amdgpu_crtc->pll_post_div;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

853

amdgpu_pll_compute(adev, pll, amdgpu_crtc->adjusted_clock, &pll_clock,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

875

(125 * 25 * pll->reference_freq / 100);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

878

(125 * 25 * pll->reference_freq / 100);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2243

int pll;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2251

pll = amdgpu_pll_get_shared_dp_ppll(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2252

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2253

return pll;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2257

pll = amdgpu_pll_get_shared_nondp_ppll(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2258

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2259

return pll;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2222

int pll;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2232

pll = amdgpu_pll_get_shared_nondp_ppll(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2233

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2234

return pll;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2151

int pll;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2159

pll = amdgpu_pll_get_shared_dp_ppll(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2160

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2161

return pll;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2165

pll = amdgpu_pll_get_shared_nondp_ppll(crtc);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2166

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2167

return pll;

sys/dev/pci/drm/i915/display/icl_dsi.c

677

struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/icl_dsi.c

686

val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1172

.pll[0] = 0x4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1173

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1174

.pll[2] = 0xB2,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1175

.pll[3] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1176

.pll[4] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1177

.pll[5] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1178

.pll[6] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1179

.pll[7] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1180

.pll[8] = 0x20,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1181

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1182

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1183

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1184

.pll[12] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1185

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1186

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1187

.pll[15] = 0xD,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1188

.pll[16] = 0x6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1189

.pll[17] = 0x8F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1190

.pll[18] = 0x84,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1191

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1198

.pll[0] = 0x34,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1199

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1200

.pll[2] = 0xC0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1201

.pll[3] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1202

.pll[4] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1203

.pll[5] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1204

.pll[6] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1205

.pll[7] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1206

.pll[8] = 0x20,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1207

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1208

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1209

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1210

.pll[12] = 0x80,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1211

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1212

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1213

.pll[15] = 0xD,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1214

.pll[16] = 0x6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1215

.pll[17] = 0xCF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1216

.pll[18] = 0x84,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1217

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1224

.pll[0] = 0xF4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1225

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1226

.pll[2] = 0x7A,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1227

.pll[3] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1228

.pll[4] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1229

.pll[5] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1230

.pll[6] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1231

.pll[7] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1232

.pll[8] = 0x20,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1233

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1234

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1235

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1236

.pll[12] = 0x58,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1237

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1238

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1239

.pll[15] = 0xB,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1240

.pll[16] = 0x6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1241

.pll[17] = 0xF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1242

.pll[18] = 0x85,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1243

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1250

.pll[0] = 0xF4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1251

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1252

.pll[2] = 0x7A,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1253

.pll[3] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1254

.pll[4] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1255

.pll[5] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1256

.pll[6] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1257

.pll[7] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1258

.pll[8] = 0x20,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1259

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1260

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1261

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1262

.pll[12] = 0x58,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1263

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1264

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1265

.pll[15] = 0xA,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1266

.pll[16] = 0x6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1267

.pll[17] = 0xF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1268

.pll[18] = 0x85,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1269

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1276

.pll[0] = 0xF4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1277

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1278

.pll[2] = 0x7A,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1279

.pll[3] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1280

.pll[4] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1281

.pll[5] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1282

.pll[6] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1283

.pll[7] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1284

.pll[8] = 0x20,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1285

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1286

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1287

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1288

.pll[12] = 0x58,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1289

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1290

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1291

.pll[15] = 0x8,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1292

.pll[16] = 0x6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1293

.pll[17] = 0xF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1294

.pll[18] = 0x85,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1295

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1303

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1304

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1305

.pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1306

.pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1313

.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1314

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1315

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1316

.pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1323

.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1324

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1325

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1326

.pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1333

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1334

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1335

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1336

.pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1343

.pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1344

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1345

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1346

.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1353

.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1354

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1355

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1356

.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1363

.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1364

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1365

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1366

.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1373

.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1374

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1375

.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1376

.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1383

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1384

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1385

.pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1386

.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1393

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1394

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1395

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1396

.pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1403

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1404

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1405

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1406

.pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1413

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1414

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1415

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1416

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1423

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1424

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1425

.pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1426

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1433

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1434

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1435

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1436

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1443

.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1444

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1445

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1446

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1453

.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1454

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1455

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1456

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1463

.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1464

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1465

.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1466

.pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1473

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1474

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1475

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1476

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1483

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1484

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1485

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1486

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1493

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1494

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1495

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1496

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1503

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1504

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1505

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1506

.pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1513

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1514

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1515

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1516

.pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1523

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1524

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1525

.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1526

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1533

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1534

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1535

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1536

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1543

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1544

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1545

.pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1546

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1553

.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1554

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1555

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1556

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1563

.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1564

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1565

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1566

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1573

.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1574

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1575

.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1576

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1583

.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1584

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1585

.pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1586

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1593

.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1594

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1595

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1596

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1603

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1604

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1605

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1606

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1613

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1614

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1615

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1616

.pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1623

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1624

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1625

.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1626

.pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1633

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1634

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1635

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1636

.pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1643

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1644

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1645

.pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1646

.pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1653

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1654

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1655

.pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1656

.pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1663

.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1664

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1665

.pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1666

.pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1673

.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1674

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1675

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1676

.pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1683

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1684

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1685

.pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1686

.pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1693

.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1694

.pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1695

.pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1696

.pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2052

drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2054

pll_state->c10.pll[i] = 0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2123

for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2124

pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2143

for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2145

pll_state->pll[i],

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2168

fracen = hw_state->pll[0] & C10_PLL0_FRACEN;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2173

frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2174

frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2175

frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2180

multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2181

hw_state->pll[2]) / 2 + 16;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2182

tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2190

BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2191

for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2194

i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2195

i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2742

if (pll_state->pll[0] & C10_PLL0_FRACEN) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2743

frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2744

frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2745

frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2748

multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2749

pll_state->pll[2]) / 2 + 16;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2751

tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2752

hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3435

for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3436

u8 expected = mpllb_sw_state->pll[i];

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3438

INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3441

expected, mpllb_hw_state->pll[i]);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3481

if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

534

.pll[0] = 0xB4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

535

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

536

.pll[2] = 0x30,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

537

.pll[3] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

538

.pll[4] = 0x26,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

539

.pll[5] = 0x0C,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

540

.pll[6] = 0x98,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

541

.pll[7] = 0x46,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

542

.pll[8] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

543

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

544

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

545

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

546

.pll[12] = 0xC0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

547

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

548

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

549

.pll[15] = 0x2,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

550

.pll[16] = 0x84,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

551

.pll[17] = 0x4F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

552

.pll[18] = 0xE5,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

553

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

560

.pll[0] = 0x4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

561

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

562

.pll[2] = 0xA2,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

563

.pll[3] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

564

.pll[4] = 0x33,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

565

.pll[5] = 0x10,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

566

.pll[6] = 0x75,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

567

.pll[7] = 0xB3,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

568

.pll[8] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

569

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

570

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

571

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

572

.pll[12] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

573

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

574

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

575

.pll[15] = 0x2,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

576

.pll[16] = 0x85,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

577

.pll[17] = 0x0F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

578

.pll[18] = 0xE6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

579

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

586

.pll[0] = 0x34,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

587

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

588

.pll[2] = 0xDA,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

589

.pll[3] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

590

.pll[4] = 0x39,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

591

.pll[5] = 0x12,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

592

.pll[6] = 0xE3,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

593

.pll[7] = 0xE9,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

594

.pll[8] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

595

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

596

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

597

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

598

.pll[12] = 0x20,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

599

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

600

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

601

.pll[15] = 0x2,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

602

.pll[16] = 0x85,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

603

.pll[17] = 0x8F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

604

.pll[18] = 0xE6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

605

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

612

.pll[0] = 0xF4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

613

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

614

.pll[2] = 0xF8,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

615

.pll[3] = 0x0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

616

.pll[4] = 0x20,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

617

.pll[5] = 0x0A,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

618

.pll[6] = 0x29,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

619

.pll[7] = 0x10,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

620

.pll[8] = 0x1, /* Verify */

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

621

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

622

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

623

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

624

.pll[12] = 0xA0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

625

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

626

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

627

.pll[15] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

628

.pll[16] = 0x84,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

629

.pll[17] = 0x4F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

630

.pll[18] = 0xE5,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

631

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

638

.pll[0] = 0xB4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

639

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

640

.pll[2] = 0x30,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

641

.pll[3] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

642

.pll[4] = 0x26,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

643

.pll[5] = 0x0C,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

644

.pll[6] = 0x98,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

645

.pll[7] = 0x46,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

646

.pll[8] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

647

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

648

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

649

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

650

.pll[12] = 0xC0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

651

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

652

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

653

.pll[15] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

654

.pll[16] = 0x85,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

655

.pll[17] = 0x4F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

656

.pll[18] = 0xE6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

657

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

664

.pll[0] = 0x4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

665

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

666

.pll[2] = 0xA2,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

667

.pll[3] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

668

.pll[4] = 0x33,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

669

.pll[5] = 0x10,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

670

.pll[6] = 0x75,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

671

.pll[7] = 0xB3,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

672

.pll[8] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

673

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

674

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

675

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

676

.pll[12] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

677

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

678

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

679

.pll[15] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

680

.pll[16] = 0x85,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

681

.pll[17] = 0x0F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

682

.pll[18] = 0xE6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

683

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

690

.pll[0] = 0xF4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

691

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

692

.pll[2] = 0xF8,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

693

.pll[3] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

694

.pll[4] = 0x20,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

695

.pll[5] = 0x0A,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

696

.pll[6] = 0x29,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

697

.pll[7] = 0x10,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

698

.pll[8] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

699

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

700

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

701

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

702

.pll[12] = 0xA0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

703

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

704

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

705

.pll[15] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

706

.pll[16] = 0x84,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

707

.pll[17] = 0x4F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

708

.pll[18] = 0xE5,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

709

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

716

.pll[0] = 0xB4,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

717

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

718

.pll[2] = 0x3E,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

719

.pll[3] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

720

.pll[4] = 0xA8,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

721

.pll[5] = 0x0C,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

722

.pll[6] = 0x33,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

723

.pll[7] = 0x54,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

724

.pll[8] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

725

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

726

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

727

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

728

.pll[12] = 0xC8,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

729

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

730

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

731

.pll[15] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

732

.pll[16] = 0x85,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

733

.pll[17] = 0x8F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

734

.pll[18] = 0xE6,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

735

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

742

.pll[0] = 0x34,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

743

.pll[1] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

744

.pll[2] = 0x84,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

745

.pll[3] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

746

.pll[4] = 0x30,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

747

.pll[5] = 0x0F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

748

.pll[6] = 0x3D,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

749

.pll[7] = 0x98,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

750

.pll[8] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

751

.pll[9] = 0x1,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

752

.pll[10] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

753

.pll[11] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

754

.pll[12] = 0xF0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

755

.pll[13] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

756

.pll[14] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

757

.pll[15] = 0,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

758

.pll[16] = 0x84,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

759

.pll[17] = 0x0F,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

760

.pll[18] = 0xE5,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

761

.pll[19] = 0x23,

sys/dev/pci/drm/i915/display/intel_ddi.c

1599

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

1602

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1607

pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1643

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

1646

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1651

RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1687

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

1690

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1698

(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||

sys/dev/pci/drm/i915/display/intel_ddi.c

1699

(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))

sys/dev/pci/drm/i915/display/intel_ddi.c

1704

DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1753

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

1756

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1761

ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),

sys/dev/pci/drm/i915/display/intel_ddi.c

1797

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

1800

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1840

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

1844

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1948

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

1951

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

1959

DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |

sys/dev/pci/drm/i915/display/intel_ddi.c

2016

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

2019

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

2022

intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));

sys/dev/pci/drm/i915/display/intel_ddi.c

243

static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_ddi.c

245

switch (pll->info->id) {

sys/dev/pci/drm/i915/display/intel_ddi.c

259

MISSING_CASE(pll->info->id);

sys/dev/pci/drm/i915/display/intel_ddi.c

267

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

269

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_ddi.c

4223

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_ddi.c

4230

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

4233

port_dpll->pll = pll;

sys/dev/pci/drm/i915/display/intel_ddi.c

4234

pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

4293

static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_ddi.c

4295

return pll->info->id == DPLL_ID_ICL_TBTPLL;

sys/dev/pci/drm/i915/display/intel_ddi.c

4303

const struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_ddi.c

4305

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

4308

if (icl_ddi_tc_pll_is_tbt(pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

4326

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_ddi.c

4333

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

4336

if (icl_ddi_tc_pll_is_tbt(pll))

sys/dev/pci/drm/i915/display/intel_ddi.c

4343

port_dpll->pll = pll;

sys/dev/pci/drm/i915/display/intel_ddi.c

4344

pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_ddi.h

43

struct intel_dpll *pll);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

623

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

632

for_each_dpll(display, pll, i) {

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

633

drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

634

pll->info->name, pll->info->id);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

636

pll->state.pipe_mask, pll->active_mask,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

637

str_yes_no(pll->on));

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

639

intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

22

#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)

sys/dev/pci/drm/i915/display/intel_display_reg_defs.h

29

#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))

sys/dev/pci/drm/i915/display/intel_display_regs.h

1755

#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1759

#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

1764

#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2404

#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2431

#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2602

#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2606

#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2607

((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2618

#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2624

#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

sys/dev/pci/drm/i915/display/intel_display_regs.h

2657

#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2663

#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2678

#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2691

#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2712

#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2739

#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2742

#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2747

#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2754

#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2757

#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2762

#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2768

#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2775

#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_regs.h

2781

#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

sys/dev/pci/drm/i915/display/intel_display_types.h

1100

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1097

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1116

pll = intel_get_dpll_by_id(display, pll_id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1118

if (!pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1121

return pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1125

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1130

switch (pll->info->id) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1177

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1224

struct intel_dpll *pll = NULL;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1227

pll = hsw_ddi_wrpll_get_dpll(state, crtc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1229

pll = hsw_ddi_lcpll_get_dpll(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1231

pll = hsw_ddi_spll_get_dpll(state, crtc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1233

if (!pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1237

pll, &crtc_state->dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1239

crtc_state->intel_dpll = pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

127

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1288

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1294

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1299

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

131

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

132

dpll_state[pll->index] = pll->state;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1367

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1370

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1381

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1386

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1388

skl_ddi_pll_write_ctrl1(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1403

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1408

skl_ddi_pll_write_ctrl1(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1412

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1415

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1423

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1428

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1433

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1466

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1471

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

165

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

168

for_each_dpll(display, pll, i) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

169

if (pll->info->id == id)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

170

return pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1739

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

179

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

185

if (drm_WARN(display->drm, !pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1887

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

189

cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

192

pll->info->name, str_on_off(state),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1942

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1945

pll = intel_find_dpll(state, crtc,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1949

pll = intel_find_dpll(state, crtc,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1954

if (!pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1958

pll, &crtc_state->dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1960

crtc_state->intel_dpll = pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1966

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1976

return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1978

return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2041

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2045

enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

208

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

211

return DG1_DPLL_ENABLE(pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

213

(pll->info->id == DPLL_ID_EHL_DPLL4))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2149

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2151

enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

216

return ICL_DPLL_ENABLE(pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2171

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2175

enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

221

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

223

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

233

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

235

if (pll->info->power_domain)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

236

pll->wakeref = intel_display_power_get(display, pll->info->power_domain);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2371

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

238

pll->info->funcs->enable(display, pll, &pll->state.hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

239

pll->on = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

243

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2440

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2445

pll = intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2448

crtc->base.base.id, crtc->base.name, pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

245

pll->info->funcs->disable(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2451

pll, &crtc_state->dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2453

crtc_state->intel_dpll = pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

246

pll->on = false;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

248

if (pll->info->power_domain)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

249

intel_display_power_put(display, pll->info->power_domain, pll->wakeref);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

262

struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

266

if (drm_WARN_ON(display->drm, !pll))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

270

old_mask = pll->active_mask;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

272

if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

273

drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

276

pll->active_mask |= pipe_mask;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2766

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

280

pll->info->name, pll->active_mask, pll->on,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2837

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

284

drm_WARN_ON(display->drm, !pll->on);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

285

assert_dpll_enabled(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

288

drm_WARN_ON(display->drm, pll->on);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

290

drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

292

_intel_enable_shared_dpll(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

308

struct intel_dpll *pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

315

if (pll == NULL)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

319

if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

320

"%s not used by [CRTC:%d:%s]\n", pll->info->name,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3210

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

326

pll->info->name, pll->active_mask, pll->on,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

329

assert_dpll_enabled(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3296

crtc_state->intel_dpll = port_dpll->pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

330

drm_WARN_ON(display->drm, !pll->on);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

332

pll->active_mask &= ~pipe_mask;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

333

if (pll->active_mask)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

336

drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

338

_intel_disable_shared_dpll(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3399

port_dpll->pll = intel_find_dpll(state, crtc,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3402

if (!port_dpll->pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3406

port_dpll->pll, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3463

port_dpll->pll = intel_find_dpll(state, crtc,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3466

if (!port_dpll->pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3469

port_dpll->pll, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

347

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3473

port_dpll->pll = intel_find_dpll(state, crtc,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3476

if (!port_dpll->pll) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3481

port_dpll->pll, &port_dpll->hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3489

intel_unreference_dpll(state, crtc, port_dpll->pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

351

for_each_dpll(display, pll, i) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

352

drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3539

new_port_dpll->pll = NULL;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

354

dpll_mask |= BIT(pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3541

if (!old_port_dpll->pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3544

intel_unreference_dpll(state, crtc, old_port_dpll->pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3549

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3553

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3559

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3616

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3620

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3631

val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3688

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3693

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3749

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3752

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3754

return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3758

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3761

return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3765

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3768

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

377

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

379

pll = intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

380

if (!pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3807

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3810

enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

384

if (dpll_state[pll->index].pipe_mask == 0) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3850

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3853

enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

386

unused_pll = pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

391

&dpll_state[pll->index].hw_state,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3915

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3926

pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3930

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3937

drm_err(display->drm, "PLL %d not locked\n", pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3940

static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3945

pll->info->id != DPLL_ID_ICL_DPLL0)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

396

pll->info->name,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3965

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3969

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

397

dpll_state[pll->index].pipe_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3971

icl_pll_power_enable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3973

icl_dpll_write(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

398

pll->active_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3981

icl_pll_enable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3983

adlp_cmtg_clock_gating_wa(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3989

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

399

return pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3994

icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3996

icl_dpll_write(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4004

icl_pll_enable(display, pll, TBT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4010

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4014

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4016

icl_pll_power_enable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4019

dkl_pll_write(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4021

icl_mg_pll_write(display, pll, hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4029

icl_pll_enable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4035

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4050

drm_err(display->drm, "PLL %d locked\n", pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4062

pll->info->id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4066

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4068

i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4070

icl_pll_disable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4074

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4076

icl_pll_disable(display, pll, TBT_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4080

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4082

i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4084

icl_pll_disable(display, pll, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

424

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

434

crtc->base.base.id, crtc->base.name, pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

440

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

447

if (dpll_state[pll->index].pipe_mask == 0)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

448

dpll_state[pll->index].hw_state = *dpll_hw_state;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4492

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4495

if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4498

return pll->info->funcs->get_freq(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

450

intel_dpll_crtc_get(crtc, pll, &dpll_state[pll->index]);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4510

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4513

return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4517

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4521

pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4523

if (pll->on && pll->info->power_domain)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4524

pll->wakeref = intel_display_power_get(display, pll->info->power_domain);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4526

pll->state.pipe_mask = 0;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4531

if (crtc_state->hw.active && crtc_state->intel_dpll == pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4532

intel_dpll_crtc_get(crtc, pll, &pll->state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4534

pll->active_mask = pll->state.pipe_mask;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4538

pll->info->name, pll->state.pipe_mask, pll->on);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4549

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4552

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4553

readout_dpll_hw_state(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4557

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4559

if (!pll->on)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4562

adlp_cmtg_clock_gating_wa(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4564

if (pll->active_mask)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4569

pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4571

_intel_disable_shared_dpll(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4576

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4581

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4582

sanitize_dpll_state(display, pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

463

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4633

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4641

active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4643

if (!pll->info->always_on) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4644

INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4646

pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4647

INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4649

pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4650

INTEL_DISPLAY_STATE_WARN(display, pll->on != active,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4652

pll->info->name, pll->on, active);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4657

pll->active_mask & ~pll->state.pipe_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4659

pll->info->name, pll->active_mask, pll->state.pipe_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4667

INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4669

pll->info->name, pipe_name(crtc->pipe), pll->active_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4671

INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4673

pll->info->name, pipe_name(crtc->pipe), pll->active_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4675

INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask),

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4677

pll->info->name, pipe_mask, pll->state.pipe_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4680

pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4683

pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4709

struct intel_dpll *pll = old_crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4711

INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4713

pll->info->name, pipe_name(crtc->pipe), pll->active_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4718

pll->state.pipe_mask & pipe_mask,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4720

pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4727

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

473

crtc->base.base.id, crtc->base.name, pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4730

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4731

verify_single_dpll_state(display, pll, NULL, NULL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

478

const struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

484

intel_dpll_crtc_put(crtc, pll, &dpll_state[pll->index]);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

518

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

524

for_each_dpll(display, pll, i)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

525

swap(pll->state, dpll_state[pll->index]);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

529

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

533

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

565

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

569

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

594

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

596

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

617

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

623

pll = intel_get_dpll_by_id(display, id);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

628

pll->info->name);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

630

pll = intel_find_dpll(state, crtc,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

636

if (!pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

641

pll, &crtc_state->dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

643

crtc_state->intel_dpll = pll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

695

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

699

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

707

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

718

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

720

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

73

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

734

struct intel_dpll *pll)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

736

enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

750

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

754

const enum intel_dpll_id id = pll->info->id;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

772

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

82

struct intel_dpll *pll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

90

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

98

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

999

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

254

u8 pll[20];

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

402

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

415

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

423

const struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

426

struct intel_dpll *pll,

sys/dev/pci/drm/i915/display/intel_pch_display.c

500

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_pch_display.c

533

pll = crtc_state->intel_dpll;

sys/dev/pci/drm/i915/display/intel_pch_display.c

535

pll_active = intel_dpll_get_hw_state(display, pll,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

504

struct intel_dpll *pll;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

540

for_each_dpll(display, pll, i) {

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

543

temp = intel_de_read(display, PCH_DPLL(pll->info->id));

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

337

pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

341

pll_state->pll[2] = REG_FIELD_PREP(C10_PLL2_MULTIPLIERL_MASK, pll_params.multiplier);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

342

pll_state->pll[3] = REG_FIELD_PREP(C10_PLL3_MULTIPLIERH_MASK, pll_params.multiplier >> 8);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

343

pll_state->pll[8] = REG_FIELD_PREP(C10_PLL8_SSC_UP_SPREAD, pll_params.ssc_up_spread);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

344

pll_state->pll[9] = REG_FIELD_PREP(C10_PLL9_FRACN_DENL_MASK, pll_params.fracn_den);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

345

pll_state->pll[10] = REG_FIELD_PREP(C10_PLL10_FRACN_DENH_MASK, pll_params.fracn_den >> 8);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

346

pll_state->pll[11] = REG_FIELD_PREP(C10_PLL11_FRACN_QUOT_L_MASK, pll_params.fracn_quot);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

347

pll_state->pll[12] = REG_FIELD_PREP(C10_PLL12_FRACN_QUOT_H_MASK,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

350

pll_state->pll[13] = REG_FIELD_PREP(C10_PLL13_FRACN_REM_L_MASK, pll_params.fracn_rem);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

351

pll_state->pll[14] = REG_FIELD_PREP(C10_PLL14_FRACN_REM_H_MASK, pll_params.fracn_rem >> 8);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

352

pll_state->pll[15] = REG_FIELD_PREP(C10_PLL15_TXCLKDIV_MASK, pll_params.tx_clk_div) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

354

pll_state->pll[16] = REG_FIELD_PREP(C10_PLL16_ANA_CPINT, pll_params.ana_cp_int) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

356

pll_state->pll[17] = REG_FIELD_PREP(C10_PLL17_ANA_CPINTGS_H_MASK, ana_cp_int_gs >> 1) |

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

358

pll_state->pll[18] =

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

362

pll_state->pll[19] = REG_FIELD_PREP(C10_PLL19_ANA_CPPROPGS_H_MASK, ana_cp_prop_gs >> 3) |

sys/dev/pci/drm/radeon/atombios_crtc.c

1063

struct radeon_pll *pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1074

pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1077

pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1082

pll = &rdev->clock.dcpll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1087

pll->flags = radeon_crtc->pll_flags;

sys/dev/pci/drm/radeon/atombios_crtc.c

1088

pll->reference_div = radeon_crtc->pll_reference_div;

sys/dev/pci/drm/radeon/atombios_crtc.c

1089

pll->post_div = radeon_crtc->pll_post_div;

sys/dev/pci/drm/radeon/atombios_crtc.c

1093

radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

1096

radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

1099

radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

1122

(125 * 25 * pll->reference_freq / 100);

sys/dev/pci/drm/radeon/atombios_crtc.c

1125

(125 * 25 * pll->reference_freq / 100);

sys/dev/pci/drm/radeon/atombios_crtc.c

1870

int pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1879

pll = radeon_get_shared_dp_ppll(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1880

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/radeon/atombios_crtc.c

1881

return pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1885

pll = radeon_get_shared_nondp_ppll(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1886

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/radeon/atombios_crtc.c

1887

return pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1927

pll = radeon_get_shared_dp_ppll(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1928

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/radeon/atombios_crtc.c

1929

return pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1933

pll = radeon_get_shared_nondp_ppll(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1934

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/radeon/atombios_crtc.c

1935

return pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1982

pll = radeon_get_shared_dp_ppll(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1983

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/radeon/atombios_crtc.c

1984

return pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1988

pll = radeon_get_shared_nondp_ppll(crtc);

sys/dev/pci/drm/radeon/atombios_crtc.c

1989

if (pll != ATOM_PPLL_INVALID)

sys/dev/pci/drm/radeon/atombios_crtc.c

1990

return pll;

sys/dev/pci/drm/radeon/radeon_display.c

1000

post_div_max = pll->post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1004

if (pll->flags & RADEON_PLL_IS_LCD) {

sys/dev/pci/drm/radeon/radeon_display.c

1005

vco_min = pll->lcd_pll_out_min;

sys/dev/pci/drm/radeon/radeon_display.c

1006

vco_max = pll->lcd_pll_out_max;

sys/dev/pci/drm/radeon/radeon_display.c

1008

vco_min = pll->pll_out_min;

sys/dev/pci/drm/radeon/radeon_display.c

1009

vco_max = pll->pll_out_max;

sys/dev/pci/drm/radeon/radeon_display.c

1012

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

sys/dev/pci/drm/radeon/radeon_display.c

1020

if (post_div_min < pll->min_post_div)

sys/dev/pci/drm/radeon/radeon_display.c

1021

post_div_min = pll->min_post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1026

if (post_div_max > pll->max_post_div)

sys/dev/pci/drm/radeon/radeon_display.c

1027

post_div_max = pll->max_post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1032

den = pll->reference_freq;

sys/dev/pci/drm/radeon/radeon_display.c

1038

if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)

sys/dev/pci/drm/radeon/radeon_display.c

1048

diff = abs(target_clock - (pll->reference_freq * fb_div) /

sys/dev/pci/drm/radeon/radeon_display.c

1052

!(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {

sys/dev/pci/drm/radeon/radeon_display.c

1069

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {

sys/dev/pci/drm/radeon/radeon_display.c

1079

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

sys/dev/pci/drm/radeon/radeon_display.c

1087

*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +

sys/dev/pci/drm/radeon/radeon_display.c

1088

(pll->reference_freq * *frac_fb_div_p)) /

sys/dev/pci/drm/radeon/radeon_display.c

1107

void radeon_compute_pll_legacy(struct radeon_pll *pll,

sys/dev/pci/drm/radeon/radeon_display.c

1115

uint32_t min_ref_div = pll->min_ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

1116

uint32_t max_ref_div = pll->max_ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

1117

uint32_t min_post_div = pll->min_post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1118

uint32_t max_post_div = pll->max_post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1121

uint32_t best_vco = pll->best_vco;

sys/dev/pci/drm/radeon/radeon_display.c

1132

DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);

sys/dev/pci/drm/radeon/radeon_display.c

1135

if (pll->flags & RADEON_PLL_IS_LCD) {

sys/dev/pci/drm/radeon/radeon_display.c

1136

pll_out_min = pll->lcd_pll_out_min;

sys/dev/pci/drm/radeon/radeon_display.c

1137

pll_out_max = pll->lcd_pll_out_max;

sys/dev/pci/drm/radeon/radeon_display.c

1139

pll_out_min = pll->pll_out_min;

sys/dev/pci/drm/radeon/radeon_display.c

1140

pll_out_max = pll->pll_out_max;

sys/dev/pci/drm/radeon/radeon_display.c

1146

if (pll->flags & RADEON_PLL_USE_REF_DIV)

sys/dev/pci/drm/radeon/radeon_display.c

1147

min_ref_div = max_ref_div = pll->reference_div;

sys/dev/pci/drm/radeon/radeon_display.c

1151

uint32_t pll_in = pll->reference_freq / mid;

sys/dev/pci/drm/radeon/radeon_display.c

1152

if (pll_in < pll->pll_in_min)

sys/dev/pci/drm/radeon/radeon_display.c

1154

else if (pll_in > pll->pll_in_max)

sys/dev/pci/drm/radeon/radeon_display.c

1161

if (pll->flags & RADEON_PLL_USE_POST_DIV)

sys/dev/pci/drm/radeon/radeon_display.c

1162

min_post_div = max_post_div = pll->post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1164

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

sys/dev/pci/drm/radeon/radeon_display.c

1165

min_fractional_feed_div = pll->min_frac_feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

1166

max_fractional_feed_div = pll->max_frac_feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

1172

if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))

sys/dev/pci/drm/radeon/radeon_display.c

1176

if (pll->flags & RADEON_PLL_LEGACY) {

sys/dev/pci/drm/radeon/radeon_display.c

1190

uint32_t pll_in = pll->reference_freq / ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

1191

uint32_t min_feed_div = pll->min_feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

1192

uint32_t max_feed_div = pll->max_feedback_div + 1;

sys/dev/pci/drm/radeon/radeon_display.c

1194

if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)

sys/dev/pci/drm/radeon/radeon_display.c

1206

tmp = (uint64_t)pll->reference_freq * feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

1219

tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

1220

tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

1223

if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {

sys/dev/pci/drm/radeon/radeon_display.c

1252

} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||

sys/dev/pci/drm/radeon/radeon_display.c

1253

((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||

sys/dev/pci/drm/radeon/radeon_display.c

1254

((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||

sys/dev/pci/drm/radeon/radeon_display.c

1255

((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||

sys/dev/pci/drm/radeon/radeon_display.c

1256

((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||

sys/dev/pci/drm/radeon/radeon_display.c

1257

((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {

sys/dev/pci/drm/radeon/radeon_display.c

956

void radeon_compute_pll_avivo(struct radeon_pll *pll,

sys/dev/pci/drm/radeon/radeon_display.c

964

unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?

sys/dev/pci/drm/radeon/radeon_display.c

974

fb_div_min = pll->min_feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

975

fb_div_max = pll->max_feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

977

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

sys/dev/pci/drm/radeon/radeon_display.c

983

if (pll->flags & RADEON_PLL_USE_REF_DIV)

sys/dev/pci/drm/radeon/radeon_display.c

984

ref_div_min = pll->reference_div;

sys/dev/pci/drm/radeon/radeon_display.c

986

ref_div_min = pll->min_ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

988

if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&

sys/dev/pci/drm/radeon/radeon_display.c

989

pll->flags & RADEON_PLL_USE_REF_DIV)

sys/dev/pci/drm/radeon/radeon_display.c

990

ref_div_max = pll->reference_div;

sys/dev/pci/drm/radeon/radeon_display.c

991

else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)

sys/dev/pci/drm/radeon/radeon_display.c

993

ref_div_max = min(pll->max_ref_div, 7u);

sys/dev/pci/drm/radeon/radeon_display.c

995

ref_div_max = pll->max_ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

998

if (pll->flags & RADEON_PLL_USE_POST_DIV) {

sys/dev/pci/drm/radeon/radeon_display.c

999

post_div_min = pll->post_div;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

751

struct radeon_pll *pll;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

774

pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

776

pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

778

pll->flags = RADEON_PLL_LEGACY;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

781

pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

783

pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

795

pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

810

pll->flags |= RADEON_PLL_USE_REF_DIV;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

818

radeon_compute_pll_legacy(pll, mode->clock,

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

849

pll_gain = radeon_compute_pll_gain(pll->reference_freq,

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

244

struct radeon_pll *pll;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

248

pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

250

pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

253

*pll_ref_freq = pll->reference_freq;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

258

if (pll->reference_freq == 2700)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

263

if (pll->reference_freq == 2700)

sys/dev/pci/drm/radeon/radeon_mode.h

774

extern void radeon_compute_pll_legacy(struct radeon_pll *pll,

sys/dev/pci/drm/radeon/radeon_mode.h

782

extern void radeon_compute_pll_avivo(struct radeon_pll *pll,

sys/dev/pci/sdhc_pci.c

325

pcireg_t misc, pll, pllssc;

sys/dev/pci/sdhc_pci.c

333

pll = pci_conf_read(sc->sc_pc, sc->sc_tag, GL9755_PLL);

sys/dev/pci/sdhc_pci.c

334

pll &= ~(GL9755_PLL_DIR | GL9755_PLL_SSC_EN);

sys/dev/pci/sdhc_pci.c

335

pci_conf_write(sc->sc_pc, sc->sc_tag, GL9755_PLL, pll);

sys/dev/pci/sdhc_pci.c

368

pll = pci_conf_read(sc->sc_pc, sc->sc_tag, GL9755_PLL);

sys/dev/pci/sdhc_pci.c

370

pll &= ~(GL9755_PLL_SSC_STEP_MASK | GL9755_PLL_SSC_EN);

sys/dev/pci/sdhc_pci.c

371

pll |= step << GL9755_PLL_SSC_STEP_SHIFT;

sys/dev/pci/sdhc_pci.c

372

pll |= enable ? GL9755_PLL_SSC_EN : 0;

sys/dev/pci/sdhc_pci.c

376

pci_conf_write(sc->sc_pc, sc->sc_tag, GL9755_PLL, pll);

sys/dev/pci/sdhc_pci.c

379

pll = pci_conf_read(sc->sc_pc, sc->sc_tag, GL9755_PLL);

sys/dev/pci/sdhc_pci.c

380

pll &= ~(GL9755_PLL_LDIV_MASK | GL9755_PLL_PDIV_MASK);

sys/dev/pci/sdhc_pci.c

381

pll &= ~GL9755_PLL_DIR;

sys/dev/pci/sdhc_pci.c

382

pll |= ldiv << GL9755_PLL_LDIV_SHIFT;

sys/dev/pci/sdhc_pci.c

383

pll |= pdiv << GL9755_PLL_PDIV_SHIFT;

sys/dev/pci/sdhc_pci.c

384

pll |= dir ? GL9755_PLL_DIR : 0;

sys/dev/pci/sdhc_pci.c

385

pci_conf_write(sc->sc_pc, sc->sc_tag, GL9755_PLL, pll);

usr.bin/netstat/inet.c

1369

pll("%lld", ssp_idletv.tv_sec, ", ");

usr.bin/netstat/unix.c

117

pll("%lld", unp_ctime.tv_sec, ", ");