Symbol: CSR_READ_4
sys/dev/ic/acx.c
1490
if (CSR_READ_4(sc, ACXREG_PHY_CTRL) == 0)
sys/dev/ic/acx.c
1693
val = CSR_READ_4(sc, ACXREG_FWMEM_DATA);
sys/dev/ic/acx.c
2456
sc->sc_cmd = CSR_READ_4(sc, ACXREG_CMD_REG_OFFSET);
sys/dev/ic/acx.c
497
sc->sc_info = CSR_READ_4(sc, ACXREG_INFO_REG_OFFSET);
sys/dev/ic/bwi.c
1046
CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */
sys/dev/ic/bwi.c
1266
state_lo = CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
1272
CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
1278
CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
1283
status = CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
1367
val = CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
1374
val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
sys/dev/ic/bwi.c
1514
CSR_READ_4(sc, BWI_MAC_STATUS); /* dummy read */
sys/dev/ic/bwi.c
1886
intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
sys/dev/ic/bwi.c
1899
CSR_READ_4(sc, BWI_MAC_INTR_STATUS); /* dummy read */
sys/dev/ic/bwi.c
2090
mac_status = CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
2286
CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
2287
CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
sys/dev/ic/bwi.c
2305
CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
2309
if (CSR_READ_4(sc, BWI_MAC_INTR_STATUS) & BWI_INTR_READY)
sys/dev/ic/bwi.c
2328
status = CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
2335
CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
2400
val = CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
2411
val = CSR_READ_4(sc, BWI_STATE_HI);
sys/dev/ic/bwi.c
2422
if (CSR_READ_4(sc, txrx_reg) & BWI_TXRX32_CTRL_ADDRHI_MASK) {
sys/dev/ic/bwi.c
2763
CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
2923
CSR_READ_4(mac->mac_sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
586
intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
sys/dev/ic/bwi.c
590
intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
sys/dev/ic/bwi.c
611
CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
sys/dev/ic/bwi.c
6355
val = CSR_READ_4(sc, BWI_ID_HI);
sys/dev/ic/bwi.c
652
if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
sys/dev/ic/bwi.c
6600
info = CSR_READ_4(sc, BWI_INFO);
sys/dev/ic/bwi.c
6605
sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
sys/dev/ic/bwi.c
6734
val = CSR_READ_4(sc, BWI_FLAGS);
sys/dev/ic/bwi.c
6793
CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
sys/dev/ic/bwi.c
6795
CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
sys/dev/ic/bwi.c
6874
val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
sys/dev/ic/bwi.c
6887
val = CSR_READ_4(sc, BWI_CLOCK_INFO);
sys/dev/ic/bwi.c
6936
clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
sys/dev/ic/bwi.c
7063
if ((CSR_READ_4(sc, BWI_TXSTATUS_0) &
sys/dev/ic/bwi.c
7066
CSR_READ_4(sc, BWI_TXSTATUS_1);
sys/dev/ic/bwi.c
7317
CSR_READ_4(sc, BWI_MAC_INTR_MASK);
sys/dev/ic/bwi.c
8488
val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
sys/dev/ic/bwi.c
8511
status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
sys/dev/ic/bwi.c
8566
val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
sys/dev/ic/bwi.c
8582
val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
sys/dev/ic/bwi.c
9049
val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
sys/dev/ic/bwi.c
9131
tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS_0);
sys/dev/ic/bwi.c
9134
tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS_1);
sys/dev/ic/bwi.c
9184
val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
sys/dev/ic/bwi.c
9237
busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
sys/dev/ic/bwi.c
9254
val = CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
9275
state_lo = CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
9299
state_lo = CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
9312
state_hi = CSR_READ_4(sc, BWI_STATE_HI);
sys/dev/ic/bwi.c
9332
CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
9341
CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
9360
CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
9363
state_hi = CSR_READ_4(sc, BWI_STATE_HI);
sys/dev/ic/bwi.c
9367
imstate = CSR_READ_4(sc, BWI_IMSTATE);
sys/dev/ic/bwi.c
9380
CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
9389
CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
998
return (CSR_READ_4(sc, BWI_MOBJ_DATA));
sys/dev/ic/bwivar.h
85
CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
sys/dev/ic/bwivar.h
90
CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
sys/dev/ic/bwivar.h
95
CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
sys/dev/ic/dc.c
1178
if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
sys/dev/ic/dc.c
1183
isr = CSR_READ_4(sc, DC_ISR);
sys/dev/ic/dc.c
1211
watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
sys/dev/ic/dc.c
1252
watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
sys/dev/ic/dc.c
1332
if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
sys/dev/ic/dc.c
1599
reg = CSR_READ_4(sc, DC_AL_PAR0);
sys/dev/ic/dc.c
1604
reg = CSR_READ_4(sc, DC_AL_PAR1);
sys/dev/ic/dc.c
196
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
sys/dev/ic/dc.c
199
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
sys/dev/ic/dc.c
210
CSR_READ_4(sc, DC_BUSCTL);
sys/dev/ic/dc.c
2308
r = CSR_READ_4(sc, DC_10BTSTAT);
sys/dev/ic/dc.c
2326
if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
sys/dev/ic/dc.c
2392
isr = CSR_READ_4(sc, DC_ISR);
sys/dev/ic/dc.c
2430
ints = CSR_READ_4(sc, DC_ISR);
sys/dev/ic/dc.c
2438
if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
sys/dev/ic/dc.c
2446
while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
sys/dev/ic/dc.c
246
if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
sys/dev/ic/dc.c
2987
isr = CSR_READ_4(sc, DC_ISR);
sys/dev/ic/dc.c
359
r = CSR_READ_4(sc, DC_SIO);
sys/dev/ic/dc.c
379
*dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
sys/dev/ic/dc.c
382
*dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
sys/dev/ic/dc.c
420
if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
sys/dev/ic/dc.c
485
CSR_READ_4(sc, DC_SIO);
sys/dev/ic/dc.c
488
if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
sys/dev/ic/dc.c
686
rval = CSR_READ_4(sc, DC_PN_MII);
sys/dev/ic/dc.c
725
rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
sys/dev/ic/dc.c
737
phy_reg = CSR_READ_4(sc, DC_NETCFG);
sys/dev/ic/dc.c
765
if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
sys/dev/ic/dc.c
809
phy_reg = CSR_READ_4(sc, DC_NETCFG);
sys/dev/ic/fxp.c
1579
while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
sys/dev/ic/fxp.c
1605
while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
sys/dev/ic/mtd8xx.c
1020
if (CSR_READ_4(MTD_TCRRCR) & TCR_ENHANCED)
sys/dev/ic/mtd8xx.c
1021
ifp->if_collisions += TSR_NCR_GET(CSR_READ_4(MTD_TSR));
sys/dev/ic/mtd8xx.c
152
enaddr[0] = letoh32(CSR_READ_4(MTD_PAR0));
sys/dev/ic/mtd8xx.c
153
enaddr[1] = letoh32(CSR_READ_4(MTD_PAR4));
sys/dev/ic/mtd8xx.c
219
miir = (CSR_READ_4(MTD_MIIMGT) & ~MIIMGT_MASK) | MIIMGT_WRITE |
sys/dev/ic/mtd8xx.c
262
miir = CSR_READ_4(MTD_MIIMGT);
sys/dev/ic/mtd8xx.c
324
rxfilt = CSR_READ_4(MTD_TCRRCR) & ~RCR_AM;
sys/dev/ic/mtd8xx.c
555
if (!(CSR_READ_4(MTD_BCR) & BCR_SWR)) {
sys/dev/ic/mtd8xx.c
816
if (CSR_READ_4(MTD_ISR) & ISR_INTRS)
sys/dev/ic/mtd8xx.c
824
while((status = CSR_READ_4(MTD_ISR)) & ISR_INTRS) {
sys/dev/ic/mtd8xxreg.h
212
#define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val))
sys/dev/ic/mtd8xxreg.h
213
#define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val))
sys/dev/ic/re.c
1968
CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
sys/dev/ic/re.c
2146
CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
sys/dev/ic/re.c
2166
if ((CSR_READ_4(sc, RL_TXCFG) &
sys/dev/ic/re.c
2513
reg = CSR_READ_4(sc, RE_DTCCR_LO);
sys/dev/ic/re.c
382
rval = CSR_READ_4(sc, RL_PHYAR);
sys/dev/ic/re.c
409
rval = CSR_READ_4(sc, RL_PHYAR);
sys/dev/ic/re.c
584
rxfilt = CSR_READ_4(sc, RL_RXCFG);
sys/dev/ic/re.c
673
sc->sc_hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
sys/dev/ic/rtl81x9.c
449
rxfilt = CSR_READ_4(sc, RL_RXCFG);
sys/dev/ic/rtl81x9.c
700
txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
sys/dev/ic/rtl81x9reg.h
987
CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
sys/dev/ic/rtl81x9reg.h
990
CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
sys/dev/ic/ti.c
1035
if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
sys/dev/ic/ti.c
1039
if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
sys/dev/ic/ti.c
1070
if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
sys/dev/ic/ti.c
1080
chip_rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK;
sys/dev/ic/ti.c
1136
cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
sys/dev/ic/ti.c
1144
if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCI_COMMAND_INVALIDATE_ENABLE) {
sys/dev/ic/ti.c
1155
CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
sys/dev/ic/ti.c
1718
if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
sys/dev/ic/ti.c
196
ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
sys/dev/ic/ti.c
2178
media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
sys/dev/ic/ti.c
2188
media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
sys/dev/ic/ti.c
220
sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
sys/dev/ic/ti.c
229
sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
sys/dev/ic/ti.c
237
sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
sys/dev/ic/ti.c
248
sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
sys/dev/ic/ti.c
259
if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
sys/dev/ic/ti.c
993
intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
sys/dev/ic/tireg.h
995
CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) | (x)))
sys/dev/ic/tireg.h
997
CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) & ~(x)))
sys/dev/ic/xl.c
1226
if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
sys/dev/ic/xl.c
1227
CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
sys/dev/ic/xl.c
1265
if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
sys/dev/ic/xl.c
1290
if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
sys/dev/ic/xl.c
1291
!CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
sys/dev/ic/xl.c
1733
if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
sys/dev/ic/xl.c
2096
icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
sys/dev/ic/xl.c
657
icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
sys/dev/ic/xl.c
679
icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
sys/dev/mii/dcphy.c
211
mode = CSR_READ_4(dc_sc, DC_NETCFG);
sys/dev/mii/dcphy.c
273
reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
sys/dev/mii/dcphy.c
319
reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
sys/dev/mii/dcphy.c
323
if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {
sys/dev/mii/dcphy.c
325
tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
sys/dev/mii/dcphy.c
377
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
sys/dev/mii/dcphy.c
382
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
sys/dev/mii/dcphy.c
412
if ((CSR_READ_4(sc, DC_10BTSTAT) & DC_TSTAT_ANEGSTAT)
sys/dev/mii/dcphy.c
69
CSR_READ_4(sc, reg) | x)
sys/dev/mii/dcphy.c
73
CSR_READ_4(sc, reg) & ~x)
sys/dev/pci/if_age.c
1086
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
1489
CSR_READ_4(sc, AGE_MASTER_CFG);
sys/dev/pci/if_age.c
1492
if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
sys/dev/pci/if_age.c
1503
CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
sys/dev/pci/if_age.c
1606
reg = CSR_READ_4(sc, AGE_MASTER_CFG);
sys/dev/pci/if_age.c
1648
CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
sys/dev/pci/if_age.c
1668
reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_age.c
1675
reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
sys/dev/pci/if_age.c
1761
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
1818
CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
sys/dev/pci/if_age.c
1822
CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
sys/dev/pci/if_age.c
1824
CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
sys/dev/pci/if_age.c
1826
if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
sys/dev/pci/if_age.c
188
sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
sys/dev/pci/if_age.c
1960
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
1966
reg = CSR_READ_4(sc, AGE_DMA_CFG);
sys/dev/pci/if_age.c
1972
if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
sys/dev/pci/if_age.c
1987
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
199
CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
sys/dev/pci/if_age.c
1993
reg = CSR_READ_4(sc, AGE_DMA_CFG);
sys/dev/pci/if_age.c
1999
if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
sys/dev/pci/if_age.c
200
CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
sys/dev/pci/if_age.c
2151
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
2169
rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
316
v = CSR_READ_4(sc, AGE_MDIO);
sys/dev/pci/if_age.c
349
v = CSR_READ_4(sc, AGE_MDIO);
sys/dev/pci/if_age.c
395
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
397
CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
sys/dev/pci/if_age.c
447
status = CSR_READ_4(sc, AGE_INTR_STATUS);
sys/dev/pci/if_age.c
513
reg = CSR_READ_4(sc, AGE_SPI_CTRL);
sys/dev/pci/if_age.c
526
CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
sys/dev/pci/if_age.c
530
reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
sys/dev/pci/if_age.c
543
ea[0] = CSR_READ_4(sc, AGE_PAR0);
sys/dev/pci/if_age.c
544
ea[1] = CSR_READ_4(sc, AGE_PAR1);
sys/dev/pci/if_alc.c
1064
pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
sys/dev/pci/if_alc.c
1102
val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
sys/dev/pci/if_alc.c
1108
CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
sys/dev/pci/if_alc.c
1110
CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
sys/dev/pci/if_alc.c
1114
val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
sys/dev/pci/if_alc.c
1146
val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
sys/dev/pci/if_alc.c
1149
val = CSR_READ_4(sc, ALC_MASTER_CFG);
sys/dev/pci/if_alc.c
1180
ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER);
sys/dev/pci/if_alc.c
1318
sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
sys/dev/pci/if_alc.c
1326
CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
sys/dev/pci/if_alc.c
1327
CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
sys/dev/pci/if_alc.c
202
v = CSR_READ_4(sc, ALC_MDIO);
sys/dev/pci/if_alc.c
2026
reg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
2074
CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
sys/dev/pci/if_alc.c
2080
CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
sys/dev/pci/if_alc.c
2108
*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
sys/dev/pci/if_alc.c
2114
*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
sys/dev/pci/if_alc.c
2201
status = CSR_READ_4(sc, ALC_INTR_STATUS);
sys/dev/pci/if_alc.c
2208
status = CSR_READ_4(sc, ALC_INTR_STATUS);
sys/dev/pci/if_alc.c
2273
prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
sys/dev/pci/if_alc.c
231
v = CSR_READ_4(sc, ALC_MDIO);
sys/dev/pci/if_alc.c
2563
reg = CSR_READ_4(sc, ALC_MISC3);
sys/dev/pci/if_alc.c
2567
reg = CSR_READ_4(sc, ALC_MISC);
sys/dev/pci/if_alc.c
2578
reg = CSR_READ_4(sc, ALC_MISC2);
sys/dev/pci/if_alc.c
2605
pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
sys/dev/pci/if_alc.c
2614
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
sys/dev/pci/if_alc.c
2621
if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
sys/dev/pci/if_alc.c
2629
if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
sys/dev/pci/if_alc.c
2636
reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
sys/dev/pci/if_alc.c
2650
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
sys/dev/pci/if_alc.c
2659
reg = CSR_READ_4(sc, ALC_MISC3);
sys/dev/pci/if_alc.c
2663
reg = CSR_READ_4(sc, ALC_MISC);
sys/dev/pci/if_alc.c
2674
CSR_READ_4(sc, ALC_SERDES_LOCK) |
sys/dev/pci/if_alc.c
271
v = CSR_READ_4(sc, ALC_MDIO);
sys/dev/pci/if_alc.c
2729
CSR_READ_4(sc, ALC_WOL_CFG);
sys/dev/pci/if_alc.c
2811
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
sys/dev/pci/if_alc.c
2935
reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_alc.c
2951
reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_alc.c
297
v = CSR_READ_4(sc, ALC_MDIO);
sys/dev/pci/if_alc.c
3091
reg = CSR_READ_4(sc, ALC_DMA_CFG);
sys/dev/pci/if_alc.c
3104
reg = CSR_READ_4(sc, ALC_PM_CFG);
sys/dev/pci/if_alc.c
3146
reg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
3152
reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
sys/dev/pci/if_alc.c
3175
cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
sys/dev/pci/if_alc.c
3184
cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
sys/dev/pci/if_alc.c
3196
reg = CSR_READ_4(sc, ALC_RXQ_CFG);
sys/dev/pci/if_alc.c
3209
reg = CSR_READ_4(sc, ALC_TXQ_CFG);
sys/dev/pci/if_alc.c
3216
reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
sys/dev/pci/if_alc.c
3324
reg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
3343
rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
342
reg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
385
v = CSR_READ_4(sc, ALC_MDIO);
sys/dev/pci/if_alc.c
416
v = CSR_READ_4(sc, ALC_MDIO);
sys/dev/pci/if_alc.c
554
opt = CSR_READ_4(sc, ALC_OPT_CFG);
sys/dev/pci/if_alc.c
555
if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
sys/dev/pci/if_alc.c
556
(CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
sys/dev/pci/if_alc.c
568
CSR_READ_4(sc, ALC_OPT_CFG);
sys/dev/pci/if_alc.c
593
CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
sys/dev/pci/if_alc.c
595
CSR_READ_4(sc, ALC_WOL_CFG);
sys/dev/pci/if_alc.c
597
CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
sys/dev/pci/if_alc.c
601
if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
sys/dev/pci/if_alc.c
619
CSR_READ_4(sc, ALC_OPT_CFG);
sys/dev/pci/if_alc.c
656
reg = CSR_READ_4(sc, ALC_SLD);
sys/dev/pci/if_alc.c
665
reg = CSR_READ_4(sc, ALC_SLD);
sys/dev/pci/if_alc.c
678
reg = CSR_READ_4(sc, ALC_EEPROM_LD);
sys/dev/pci/if_alc.c
682
reg = CSR_READ_4(sc, ALC_EEPROM_LD);
sys/dev/pci/if_alc.c
693
reg = CSR_READ_4(sc, ALC_EEPROM_LD);
sys/dev/pci/if_alc.c
711
ea[0] = CSR_READ_4(sc, ALC_PAR0);
sys/dev/pci/if_alc.c
712
ea[1] = CSR_READ_4(sc, ALC_PAR1);
sys/dev/pci/if_alc.c
728
pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
sys/dev/pci/if_alc.c
866
val = CSR_READ_4(sc, ALC_GPHY_CFG);
sys/dev/pci/if_alc.c
885
val = CSR_READ_4(sc, ALC_LPI_CTL);
sys/dev/pci/if_alc.c
931
gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
sys/dev/pci/if_alc.c
982
pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
sys/dev/pci/if_ale.c
1105
reg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
1136
CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
sys/dev/pci/if_ale.c
1141
CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
sys/dev/pci/if_ale.c
1160
*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
sys/dev/pci/if_ale.c
1165
*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
sys/dev/pci/if_ale.c
1242
status = CSR_READ_4(sc, ALE_INTR_STATUS);
sys/dev/pci/if_ale.c
146
v = CSR_READ_4(sc, ALE_MDIO);
sys/dev/pci/if_ale.c
1556
CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
sys/dev/pci/if_ale.c
1561
if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
sys/dev/pci/if_ale.c
1568
if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
sys/dev/pci/if_ale.c
1611
CSR_READ_4(sc, ALE_WOL_CFG);
sys/dev/pci/if_ale.c
1670
reg = CSR_READ_4(sc, ALE_MASTER_CFG);
sys/dev/pci/if_ale.c
1734
reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_ale.c
175
v = CSR_READ_4(sc, ALE_MDIO);
sys/dev/pci/if_ale.c
1845
reg = CSR_READ_4(sc, ALE_TXQ_CFG);
sys/dev/pci/if_ale.c
1848
reg = CSR_READ_4(sc, ALE_RXQ_CFG);
sys/dev/pci/if_ale.c
1851
reg = CSR_READ_4(sc, ALE_DMA_CFG);
sys/dev/pci/if_ale.c
1883
reg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
1890
reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
sys/dev/pci/if_ale.c
1955
reg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
1973
rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
222
reg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
273
reg = CSR_READ_4(sc, ALE_SPI_CTRL);
sys/dev/pci/if_ale.c
285
CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
sys/dev/pci/if_ale.c
289
reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
sys/dev/pci/if_ale.c
302
ea[0] = CSR_READ_4(sc, ALE_PAR0);
sys/dev/pci/if_ale.c
303
ea[1] = CSR_READ_4(sc, ALE_PAR1);
sys/dev/pci/if_ale.c
422
if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
sys/dev/pci/if_ale.c
455
sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
sys/dev/pci/if_ale.c
468
txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
sys/dev/pci/if_ale.c
469
rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_bge.c
1014
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
sys/dev/pci/if_bge.c
1023
CSR_READ_4(sc, BGE_MI_COMM); /* force write */
sys/dev/pci/if_bge.c
1027
val = CSR_READ_4(sc, BGE_MI_COMM);
sys/dev/pci/if_bge.c
1039
val = CSR_READ_4(sc, BGE_MI_COMM);
sys/dev/pci/if_bge.c
1071
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
sys/dev/pci/if_bge.c
1081
CSR_READ_4(sc, BGE_MI_COMM); /* force write */
sys/dev/pci/if_bge.c
1085
if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
sys/dev/pci/if_bge.c
1130
mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
sys/dev/pci/if_bge.c
1132
tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
sys/dev/pci/if_bge.c
1133
rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
sys/dev/pci/if_bge.c
1583
rxmode = CSR_READ_4(sc, BGE_RX_MODE) & ~BGE_RXMODE_RX_PROMISC;
sys/dev/pci/if_bge.c
1665
phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) &
sys/dev/pci/if_bge.c
1668
phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
sys/dev/pci/if_bge.c
1714
CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
sys/dev/pci/if_bge.c
1757
tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
sys/dev/pci/if_bge.c
1809
mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
sys/dev/pci/if_bge.c
1855
CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
sys/dev/pci/if_bge.c
1933
if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
sys/dev/pci/if_bge.c
1950
if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
sys/dev/pci/if_bge.c
2093
(CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
sys/dev/pci/if_bge.c
2211
val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
sys/dev/pci/if_bge.c
2236
if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
sys/dev/pci/if_bge.c
2367
val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
sys/dev/pci/if_bge.c
2385
dmactl = CSR_READ_4(sc, rdmareg);
sys/dev/pci/if_bge.c
2410
CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
sys/dev/pci/if_bge.c
2419
CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
sys/dev/pci/if_bge.c
2424
CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
sys/dev/pci/if_bge.c
2434
val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
sys/dev/pci/if_bge.c
2441
val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
sys/dev/pci/if_bge.c
2810
misccfg = CSR_READ_4(sc, BGE_MISC_CFG);
sys/dev/pci/if_bge.c
3126
CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
sys/dev/pci/if_bge.c
3280
mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
sys/dev/pci/if_bge.c
3296
if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
sys/dev/pci/if_bge.c
3333
if (CSR_READ_4(sc, 0x7e2c) == 0x60) {
sys/dev/pci/if_bge.c
3349
val = CSR_READ_4(sc, BGE_VCPU_STATUS);
sys/dev/pci/if_bge.c
3352
val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
sys/dev/pci/if_bge.c
3422
val = CSR_READ_4(sc, BGE_MSI_MODE);
sys/dev/pci/if_bge.c
3426
val = CSR_READ_4(sc, BGE_MARB_MODE);
sys/dev/pci/if_bge.c
3434
val = CSR_READ_4(sc, BGE_MAC_MODE);
sys/dev/pci/if_bge.c
3443
val = CSR_READ_4(sc, BGE_VCPU_STATUS);
sys/dev/pci/if_bge.c
3481
val = CSR_READ_4(sc, BGE_SERDES_CFG);
sys/dev/pci/if_bge.c
3491
val = CSR_READ_4(sc, 0x7c00);
sys/dev/pci/if_bge.c
3769
(CSR_READ_4(sc, BGE_PCI_PCISTATE) &
sys/dev/pci/if_bge.c
3775
(CSR_READ_4(sc, BGE_PCI_PCISTATE) &
sys/dev/pci/if_bge.c
3863
collisions = CSR_READ_4(sc, BGE_MAC_STATS +
sys/dev/pci/if_bge.c
3887
discards = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
sys/dev/pci/if_bge.c
3891
inerrors = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
sys/dev/pci/if_bge.c
3896
ucast = CSR_READ_4(sc, BGE_MAC_STATS +
sys/dev/pci/if_bge.c
3898
mcast = CSR_READ_4(sc, BGE_MAC_STATS +
sys/dev/pci/if_bge.c
3900
bcast = CSR_READ_4(sc, BGE_MAC_STATS +
sys/dev/pci/if_bge.c
3909
val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
sys/dev/pci/if_bge.c
3937
CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
sys/dev/pci/if_bge.c
4354
mode = CSR_READ_4(sc, BGE_TX_MODE);
sys/dev/pci/if_bge.c
4361
mode |= CSR_READ_4(sc, BGE_TX_MODE) &
sys/dev/pci/if_bge.c
4369
mode = CSR_READ_4(sc, BGE_RX_MODE);
sys/dev/pci/if_bge.c
4431
sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
sys/dev/pci/if_bge.c
4434
sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
sys/dev/pci/if_bge.c
4499
if (CSR_READ_4(sc, BGE_MAC_STS) &
sys/dev/pci/if_bge.c
4507
if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
sys/dev/pci/if_bge.c
4648
if ((CSR_READ_4(sc, reg) & bit) == 0)
sys/dev/pci/if_bge.c
4798
status = CSR_READ_4(sc, BGE_MAC_STS);
sys/dev/pci/if_bge.c
4823
status = CSR_READ_4(sc, BGE_MAC_STS);
sys/dev/pci/if_bge.c
4831
status = CSR_READ_4(sc, BGE_MAC_MODE);
sys/dev/pci/if_bge.c
4856
link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)?
sys/dev/pci/if_bge.c
4992
kstat_kv_u32(kvs) += CSR_READ_4(sc,
sys/dev/pci/if_bge.c
874
if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
sys/dev/pci/if_bge.c
882
access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
sys/dev/pci/if_bge.c
889
if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
sys/dev/pci/if_bge.c
901
byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
sys/dev/pci/if_bge.c
910
CSR_READ_4(sc, BGE_NVRAM_SWARB);
sys/dev/pci/if_bge.c
967
if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
sys/dev/pci/if_bge.c
977
byte = CSR_READ_4(sc, BGE_EE_DATA);
sys/dev/pci/if_bgereg.h
2280
val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0x7FFF)); \
sys/dev/pci/if_bgereg.h
2740
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
sys/dev/pci/if_bgereg.h
2742
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
sys/dev/pci/if_bwi_pci.c
119
for (i = 0; CSR_READ_4(sc, BWI_RESET_STATUS) && i < 30; i++)
sys/dev/pci/if_bwi_pci.c
123
CSR_READ_4(sc, BWI_RESET_CTRL);
sys/dev/pci/if_bwi_pci.c
126
CSR_READ_4(sc, BWI_RESET_CTRL);
sys/dev/pci/if_et.c
1115
if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {
sys/dev/pci/if_et.c
1189
pktfilt = CSR_READ_4(sc, ET_PKTFILT);
sys/dev/pci/if_et.c
1190
rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);
sys/dev/pci/if_et.c
1610
if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {
sys/dev/pci/if_et.c
1631
val = CSR_READ_4(sc, ET_MAC_CFG1);
sys/dev/pci/if_et.c
1642
val = CSR_READ_4(sc, ET_MAC_CFG1);
sys/dev/pci/if_et.c
1883
tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);
sys/dev/pci/if_et.c
325
val = CSR_READ_4(sc, ET_MII_IND);
sys/dev/pci/if_et.c
339
val = CSR_READ_4(sc, ET_MII_STAT);
sys/dev/pci/if_et.c
368
val = CSR_READ_4(sc, ET_MII_IND);
sys/dev/pci/if_et.c
392
cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
sys/dev/pci/if_et.c
398
ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
sys/dev/pci/if_et.c
922
intrs = CSR_READ_4(sc, ET_INTR_STATUS);
sys/dev/pci/if_ipw.c
1026
r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX);
sys/dev/pci/if_ipw.c
1050
if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff)
sys/dev/pci/if_ipw.c
120
return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA);
sys/dev/pci/if_ipw.c
1381
(CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ?
sys/dev/pci/if_ipw.c
1449
if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED)
sys/dev/pci/if_ipw.c
1457
tmp = CSR_READ_4(sc, IPW_CSR_RST);
sys/dev/pci/if_ipw.c
1470
tmp = CSR_READ_4(sc, IPW_CSR_CTL);
sys/dev/pci/if_ipw.c
1475
if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY)
sys/dev/pci/if_ipw.c
1482
tmp = CSR_READ_4(sc, IPW_CSR_RST);
sys/dev/pci/if_ipw.c
1487
tmp = CSR_READ_4(sc, IPW_CSR_CTL);
sys/dev/pci/if_ipw.c
1578
tmp = CSR_READ_4(sc, IPW_CSR_CTL);
sys/dev/pci/if_ipw.c
1588
tmp = CSR_READ_4(sc, IPW_CSR_IO);
sys/dev/pci/if_ipw.c
1988
sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE);
sys/dev/pci/if_ipw.c
1989
sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE);
sys/dev/pci/if_ipw.c
933
r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX);
sys/dev/pci/if_iwi.c
1087
hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX);
sys/dev/pci/if_iwi.c
1130
hw = CSR_READ_4(sc, txq->csr_ridx);
sys/dev/pci/if_iwi.c
1157
if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff)
sys/dev/pci/if_iwi.c
125
return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA);
sys/dev/pci/if_iwi.c
1477
(CSR_READ_4(sc, IWI_CSR_IO) & IWI_IO_RADIO_ENABLED) ?
sys/dev/pci/if_iwi.c
1508
if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)
sys/dev/pci/if_iwi.c
1517
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1530
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/pci/if_iwi.c
1537
if (CSR_READ_4(sc, IWI_CSR_CTL) & IWI_CTL_CLOCK_READY)
sys/dev/pci/if_iwi.c
1547
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1552
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/pci/if_iwi.c
1570
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1573
if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)
sys/dev/pci/if_iwi.c
1586
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1717
sentinel = CSR_READ_4(sc, IWI_CSR_AUTOINC_ADDR);
sys/dev/pci/if_iwi.c
1720
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1748
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/pci/if_iwi.c
667
val = CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE);
sys/dev/pci/if_jme.c
1074
gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
sys/dev/pci/if_jme.c
1075
pmcs = CSR_READ_4(sc, JME_PMCS);
sys/dev/pci/if_jme.c
1348
rxmac = CSR_READ_4(sc, JME_RXMAC);
sys/dev/pci/if_jme.c
1350
txmac = CSR_READ_4(sc, JME_TXMAC);
sys/dev/pci/if_jme.c
1352
txpause = CSR_READ_4(sc, JME_TXPFC);
sys/dev/pci/if_jme.c
1365
CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
sys/dev/pci/if_jme.c
1371
CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
sys/dev/pci/if_jme.c
1378
gp1 = CSR_READ_4(sc, JME_GPREG1);
sys/dev/pci/if_jme.c
1445
status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
sys/dev/pci/if_jme.c
1452
status = CSR_READ_4(sc, JME_INTR_STATUS);
sys/dev/pci/if_jme.c
155
if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
sys/dev/pci/if_jme.c
186
if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
sys/dev/pci/if_jme.c
1906
reg = CSR_READ_4(sc, JME_PMCS);
sys/dev/pci/if_jme.c
1915
reg = CSR_READ_4(sc, JME_RXMAC);
sys/dev/pci/if_jme.c
1921
reg = CSR_READ_4(sc, JME_GPREG0);
sys/dev/pci/if_jme.c
2031
CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
sys/dev/pci/if_jme.c
2079
reg = CSR_READ_4(sc, JME_TXCSR);
sys/dev/pci/if_jme.c
2086
if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
sys/dev/pci/if_jme.c
2100
reg = CSR_READ_4(sc, JME_RXCSR);
sys/dev/pci/if_jme.c
2107
if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
sys/dev/pci/if_jme.c
2241
reg = CSR_READ_4(sc, JME_RXMAC);
sys/dev/pci/if_jme.c
2259
rxcfg = CSR_READ_4(sc, JME_RXMAC);
sys/dev/pci/if_jme.c
368
reg = CSR_READ_4(sc, JME_SMBCSR);
sys/dev/pci/if_jme.c
383
reg = CSR_READ_4(sc, JME_SMBINTF);
sys/dev/pci/if_jme.c
393
reg = CSR_READ_4(sc, JME_SMBINTF);
sys/dev/pci/if_jme.c
449
par0 = CSR_READ_4(sc, JME_PAR0);
sys/dev/pci/if_jme.c
450
par1 = CSR_READ_4(sc, JME_PAR1);
sys/dev/pci/if_jme.c
591
reg = CSR_READ_4(sc, JME_CHIPMODE);
sys/dev/pci/if_jme.c
614
reg = CSR_READ_4(sc, JME_SMBCSR);
sys/dev/pci/if_jme.c
633
sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
sys/dev/pci/if_lge.c
161
CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_lge.c
165
CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_lge.c
168
CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
sys/dev/pci/if_lge.c
171
CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
sys/dev/pci/if_lge.c
186
if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
sys/dev/pci/if_lge.c
194
val = CSR_READ_4(sc, LGE_EEDATA);
sys/dev/pci/if_lge.c
239
if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
sys/dev/pci/if_lge.c
247
return (CSR_READ_4(sc, LGE_GMIICTL) >> 16);
sys/dev/pci/if_lge.c
260
if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
sys/dev/pci/if_lge.c
352
if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
sys/dev/pci/if_lge.c
504
if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
sys/dev/pci/if_lge.c
611
CSR_READ_4(sc, LGE_ISR);
sys/dev/pci/if_lge.c
804
ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
sys/dev/pci/if_lge.c
806
ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
sys/dev/pci/if_lge.c
846
status = CSR_READ_4(sc, LGE_ISR);
sys/dev/pci/if_msk.c
1894
status = CSR_READ_4(sc, SK_Y2_ISSR2);
sys/dev/pci/if_msk.c
1902
status = CSR_READ_4(sc, SK_ISR);
sys/dev/pci/if_msk.c
1992
CSR_READ_4(sc_if->sk_softc, SK_CSR)));
sys/dev/pci/if_msk.c
347
return CSR_READ_4(sc, reg);
sys/dev/pci/if_nge.c
1182
bmsr = CSR_READ_4(sc, NGE_TBI_BMSR);
sys/dev/pci/if_nge.c
1193
anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR);
sys/dev/pci/if_nge.c
1194
txcfg = CSR_READ_4(sc, NGE_TX_CFG);
sys/dev/pci/if_nge.c
1195
rxcfg = CSR_READ_4(sc, NGE_RX_CFG);
sys/dev/pci/if_nge.c
1258
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
sys/dev/pci/if_nge.c
1263
status = CSR_READ_4(sc, NGE_ISR);
sys/dev/pci/if_nge.c
1314
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
sys/dev/pci/if_nge.c
1561
txcfg = CSR_READ_4(sc, NGE_TX_CFG);
sys/dev/pci/if_nge.c
1562
rxcfg = CSR_READ_4(sc, NGE_RX_CFG);
sys/dev/pci/if_nge.c
1592
CSR_READ_4(sc, NGE_CFG)));
sys/dev/pci/if_nge.c
1677
anar = CSR_READ_4(sc, NGE_TBI_ANAR);
sys/dev/pci/if_nge.c
1681
bmcr = CSR_READ_4(sc, NGE_TBI_BMCR);
sys/dev/pci/if_nge.c
1689
txcfg = CSR_READ_4(sc, NGE_TX_CFG);
sys/dev/pci/if_nge.c
1690
rxcfg = CSR_READ_4(sc, NGE_RX_CFG);
sys/dev/pci/if_nge.c
1720
bmcr = CSR_READ_4(sc, NGE_TBI_BMCR);
sys/dev/pci/if_nge.c
1723
u_int32_t bmsr = CSR_READ_4(sc, NGE_TBI_BMSR);
sys/dev/pci/if_nge.c
1744
u_int32_t anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR);
sys/dev/pci/if_nge.c
182
CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_nge.c
186
CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_nge.c
189
CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
sys/dev/pci/if_nge.c
192
CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
sys/dev/pci/if_nge.c
200
CSR_READ_4(sc, NGE_CSR);
sys/dev/pci/if_nge.c
284
if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
sys/dev/pci/if_nge.c
403
ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
sys/dev/pci/if_nge.c
425
if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
sys/dev/pci/if_nge.c
535
txcfg = CSR_READ_4(sc, NGE_TX_CFG);
sys/dev/pci/if_nge.c
536
rxcfg = CSR_READ_4(sc, NGE_RX_CFG);
sys/dev/pci/if_nge.c
591
filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
sys/dev/pci/if_nge.c
628
if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
sys/dev/pci/if_nge.c
805
if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
sys/dev/pci/if_nge.c
820
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
sys/dev/pci/if_se.c
1050
status = CSR_READ_4(sc, IntrStatus);
sys/dev/pci/if_se.c
1072
status = CSR_READ_4(sc, IntrStatus);
sys/dev/pci/if_se.c
1417
CSR_READ_4(sc, IntrMask);
sys/dev/pci/if_se.c
215
val = CSR_READ_4(sc, ROMInterface);
sys/dev/pci/if_se.c
324
val = CSR_READ_4(sc, GMIIControl);
sys/dev/pci/if_se.c
418
ctl = CSR_READ_4(sc, StationControl);
sys/dev/pci/if_se.c
491
CSR_READ_4(sc, IntrControl);
sys/dev/pci/if_sis.c
1042
sc->sis_srr = CSR_READ_4(sc, NS_SRR);
sys/dev/pci/if_sis.c
150
CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_sis.c
154
CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_sis.c
1546
status = CSR_READ_4(sc, SIS_ISR);
sys/dev/pci/if_sis.c
157
CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
sys/dev/pci/if_sis.c
160
CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
sys/dev/pci/if_sis.c
1815
if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
sys/dev/pci/if_sis.c
189
CSR_READ_4(sc, SIS_CSR);
sys/dev/pci/if_sis.c
1990
CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
sys/dev/pci/if_sis.c
272
if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
sys/dev/pci/if_sis.c
331
rxfilt = CSR_READ_4(sc, SIS_RXFILT_CTL);
sys/dev/pci/if_sis.c
332
csrsave = CSR_READ_4(sc, SIS_CSR);
sys/dev/pci/if_sis.c
340
enaddr[0] = letoh16(CSR_READ_4(sc, SIS_RXFILT_DATA) & 0xffff);
sys/dev/pci/if_sis.c
342
enaddr[1] = letoh16(CSR_READ_4(sc, SIS_RXFILT_DATA) & 0xffff);
sys/dev/pci/if_sis.c
344
enaddr[2] = letoh16(CSR_READ_4(sc, SIS_RXFILT_DATA) & 0xffff);
sys/dev/pci/if_sis.c
358
if ((CSR_READ_4(sc, SIS_EECTL) & SIS96x_EECTL_GNT)) {
sys/dev/pci/if_sis.c
454
ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
sys/dev/pci/if_sis.c
476
if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
sys/dev/pci/if_sis.c
564
if (!CSR_READ_4(sc, NS_BMSR))
sys/dev/pci/if_sis.c
566
return CSR_READ_4(sc, NS_BMCR + (reg * 4));
sys/dev/pci/if_sis.c
586
if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
sys/dev/pci/if_sis.c
596
val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
sys/dev/pci/if_sis.c
643
if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
sys/dev/pci/if_sis.c
727
reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
sys/dev/pci/if_sis.c
730
reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
sys/dev/pci/if_sis.c
788
rxfilt = CSR_READ_4(sc, SIS_RXFILT_CTL);
sys/dev/pci/if_sis.c
794
CSR_READ_4(sc, SIS_RXFILT_CTL);
sys/dev/pci/if_sis.c
848
CSR_READ_4(sc, SIS_RXFILT_CTL);
sys/dev/pci/if_sis.c
868
rxfilt = CSR_READ_4(sc, SIS_RXFILT_CTL);
sys/dev/pci/if_sis.c
874
CSR_READ_4(sc, SIS_RXFILT_CTL);
sys/dev/pci/if_sis.c
916
CSR_READ_4(sc, SIS_RXFILT_CTL);
sys/dev/pci/if_sis.c
927
if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
sys/dev/pci/if_sk.c
1858
status = CSR_READ_4(sc, SK_ISSR);
sys/dev/pci/if_sk.c
1921
status = CSR_READ_4(sc, SK_ISSR);
sys/dev/pci/if_sk.c
205
return CSR_READ_4(sc, reg);
sys/dev/pci/if_sk.c
2093
CSR_READ_4(sc_if->sk_softc, SK_CSR)));
sys/dev/pci/if_sk.c
2361
CSR_READ_4(sc, SK_ISSR);
sys/dev/pci/if_sk.c
2424
val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
sys/dev/pci/if_ste.c
113
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
sys/dev/pci/if_ste.c
116
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
sys/dev/pci/if_ste.c
1179
if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
sys/dev/pci/if_ste.c
426
if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
sys/dev/pci/if_stge.c
1024
(void) CSR_READ_4(sc, STGE_OctetRcvOk);
sys/dev/pci/if_stge.c
1029
(void) CSR_READ_4(sc, STGE_OctetXmtdOk);
sys/dev/pci/if_stge.c
1032
CSR_READ_4(sc, STGE_LateCollisions) +
sys/dev/pci/if_stge.c
1033
CSR_READ_4(sc, STGE_MultiColFrames) +
sys/dev/pci/if_stge.c
1034
CSR_READ_4(sc, STGE_SingleColFrames);
sys/dev/pci/if_stge.c
1052
ac = CSR_READ_4(sc, STGE_AsicCtrl);
sys/dev/pci/if_stge.c
1068
if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
sys/dev/pci/if_stge.c
283
if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
sys/dev/pci/if_stge.c
437
if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
sys/dev/pci/if_stge.c
755
txstat = CSR_READ_4(sc, STGE_TxStatus);
sys/dev/pci/if_tl.c
1187
cmd = CSR_READ_4(sc, TL_HOSTCMD);
sys/dev/pci/if_tl.c
1206
(unsigned int)CSR_READ_4(sc, TL_CH_PARM));
sys/dev/pci/if_tl.c
1320
*p++ = CSR_READ_4(sc, TL_DIO_DATA);
sys/dev/pci/if_tl.c
1321
*p++ = CSR_READ_4(sc, TL_DIO_DATA);
sys/dev/pci/if_tl.c
1322
*p++ = CSR_READ_4(sc, TL_DIO_DATA);
sys/dev/pci/if_tl.c
1323
*p++ = CSR_READ_4(sc, TL_DIO_DATA);
sys/dev/pci/if_tl.c
1324
*p++ = CSR_READ_4(sc, TL_DIO_DATA);
sys/dev/pci/if_tl.c
1516
cmd = CSR_READ_4(sc, TL_HOSTCMD);
sys/dev/pci/if_tl.c
309
return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
sys/dev/pci/if_tl.c
892
cmd = CSR_READ_4(sc, TL_HOSTCMD);
sys/dev/pci/if_tlreg.h
516
CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))
sys/dev/pci/if_tlreg.h
518
CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))
sys/dev/pci/if_vge.c
1256
status = CSR_READ_4(sc, VGE_ISR);
sys/dev/pci/if_vgevar.h
118
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_vgevar.h
125
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_vr.c
195
CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_vr.c
199
CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_wb.c
1064
status = CSR_READ_4(sc, WB_ISR);
sys/dev/pci/if_wb.c
164
CSR_READ_4(sc, reg) | x)
sys/dev/pci/if_wb.c
168
CSR_READ_4(sc, reg) & ~x)
sys/dev/pci/if_wb.c
172
CSR_READ_4(sc, WB_SIO) | x)
sys/dev/pci/if_wb.c
176
CSR_READ_4(sc, WB_SIO) & ~x)
sys/dev/pci/if_wb.c
232
if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
sys/dev/pci/if_wb.c
356
ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
sys/dev/pci/if_wb.c
382
if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
sys/dev/pci/if_wb.c
508
rxfilt = CSR_READ_4(sc, WB_NETCFG);
sys/dev/pci/if_wb.c
559
if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
sys/dev/pci/if_wb.c
565
if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
sys/dev/pci/if_wb.c
566
(CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
sys/dev/pci/if_wb.c
607
if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
sys/dev/pci/if_wb.c
957
if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)