sys/dev/ic/acx.c

1097

intr_status = CSR_READ_2(sc, ACXREG_INTR_STATUS_CLR);

sys/dev/ic/acx.c

1433

reg = CSR_READ_2(sc, ACXREG_SOFT_RESET);

sys/dev/ic/acx.c

1443

reg = CSR_READ_2(sc, ACXREG_ECPU_CTRL);

sys/dev/ic/acx.c

1463

if (CSR_READ_2(sc, ACXREG_EEPROM_CTRL) == 0)

sys/dev/ic/acx.c

1548

reg = CSR_READ_2(sc, ACXREG_INTR_STATUS);

sys/dev/ic/acx.c

244

ee_info = CSR_READ_2(sc, ACXREG_EEPROM_INFO);

sys/dev/ic/acx.c

2626

reg = CSR_READ_2(sc, ACXREG_INTR_STATUS);

sys/dev/ic/acxvar.h

94

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b))

sys/dev/ic/acxvar.h

96

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b)))

sys/dev/ic/an.c

356

fid = CSR_READ_2(sc, AN_RX_FID);

sys/dev/ic/an.c

492

id = CSR_READ_2(sc, AN_TX_CMP_FID);

sys/dev/ic/an.c

543

if (CSR_READ_2(sc, AN_SW0) != AN_MAGIC) {

sys/dev/ic/an.c

545

CSR_READ_2(sc, AN_SW0)));

sys/dev/ic/an.c

549

status = CSR_READ_2(sc, AN_EVENT_STAT);

sys/dev/ic/an.c

579

if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY) {

sys/dev/ic/an.c

582

CSR_READ_2(sc, AN_COMMAND));

sys/dev/ic/an.c

597

if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD)

sys/dev/ic/an.c

602

stat = CSR_READ_2(sc, AN_STATUS);

sys/dev/ic/an.c

605

if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY)

sys/dev/ic/an.c

622

CSR_READ_2(sc, AN_RESP0), CSR_READ_2(sc, AN_RESP1),

sys/dev/ic/an.c

623

CSR_READ_2(sc, AN_RESP2));

sys/dev/ic/an.c

658

status = CSR_READ_2(sc, AN_LINKSTAT);

sys/dev/ic/an.c

685

if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD)

sys/dev/ic/an.c

709

(void) CSR_READ_2(sc, AN_DATA0);

sys/dev/ic/an.c

744

status = CSR_READ_2(sc, AN_OFF0);

sys/dev/ic/an.c

815

if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_ALLOC)

sys/dev/ic/an.c

824

*idp = CSR_READ_2(sc, AN_ALLOC_FID);

sys/dev/ic/bwi.c

1531

if (CSR_READ_2(sc, 0x50e) & 0x80)

sys/dev/ic/bwi.c

1536

if (CSR_READ_2(sc, 0x50e) & 0x400)

sys/dev/ic/bwi.c

1541

if ((CSR_READ_2(sc, 0x690) & 0x100) == 0)

sys/dev/ic/bwi.c

2776

CSR_READ_2(sc, BWI_PHYINFO); /* dummy read */

sys/dev/ic/bwi.c

2824

return (CSR_READ_2(sc, BWI_PHY_DATA));

sys/dev/ic/bwi.c

2837

val = CSR_READ_2(sc, BWI_PHYINFO);

sys/dev/ic/bwi.c

3756

return (CSR_READ_2(sc, BWI_RF_DATA_LO));

sys/dev/ic/bwi.c

3787

val = CSR_READ_2(sc, BWI_RF_DATA_HI);

sys/dev/ic/bwi.c

3791

val |= CSR_READ_2(sc, BWI_RF_DATA_LO);

sys/dev/ic/bwi.c

4316

bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);

sys/dev/ic/bwi.c

4353

bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);

sys/dev/ic/bwi.c

4354

rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);

sys/dev/ic/bwi.c

4805

ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);

sys/dev/ic/bwi.c

4807

chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);

sys/dev/ic/bwi.c

5185

ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);

sys/dev/ic/bwi.c

5186

bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);

sys/dev/ic/bwi.c

5187

chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);

sys/dev/ic/bwi.c

5460

ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);

sys/dev/ic/bwi.c

5468

bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);

sys/dev/ic/bwi.c

5469

chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);

sys/dev/ic/bwi.c

6111

bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);

sys/dev/ic/bwi.c

6206

return (CSR_READ_2(sc, ofs + BWI_SPROM_START));

sys/dev/ic/bwi.c

6453

val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);

sys/dev/ic/bwi.c

6539

val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);

sys/dev/ic/bwi.c

6560

val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);

sys/dev/ic/bwi.c

974

return (CSR_READ_2(sc, data_reg));

sys/dev/ic/bwi.c

988

ret = CSR_READ_2(sc, BWI_MOBJ_DATA_UNALIGN);

sys/dev/ic/bwi.c

993

ret |= CSR_READ_2(sc, BWI_MOBJ_DATA);

sys/dev/ic/bwivar.h

87

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))

sys/dev/ic/bwivar.h

92

CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

97

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))

sys/dev/ic/fxp.c

1421

CSR_READ_2(sc, FXP_CSR_SCB_COMMAND) |

sys/dev/ic/fxp.c

1718

for (i = FXP_CMD_TMO; (CSR_READ_2(sc, FXP_CSR_SCB_STATUS) &

sys/dev/ic/fxp.c

1721

if ((CSR_READ_2(sc, FXP_CSR_SCB_STATUS) &

sys/dev/ic/fxp.c

192

while ((CSR_READ_2(sc, FXP_CSR_SCB_COMMAND) & 0xff) && --i)

sys/dev/ic/fxp.c

249

if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)

sys/dev/ic/fxp.c

582

if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0)

sys/dev/ic/fxp.c

649

if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &

sys/dev/ic/fxp.c

780

statack = CSR_READ_2(sc, FXP_CSR_SCB_STATUS);

sys/dev/ic/fxp.c

789

while ((statack = CSR_READ_2(sc, FXP_CSR_SCB_STATUS)) &

sys/dev/ic/fxp.c

980

if (!(CSR_READ_2(sc, FXP_CSR_SCB_COMMAND) & 0xff)) {

sys/dev/ic/if_wi.c

1069

len = CSR_READ_2(sc, WI_DATA1);

sys/dev/ic/if_wi.c

1072

code = CSR_READ_2(sc, WI_DATA1);

sys/dev/ic/if_wi.c

1275

if (!(CSR_READ_2(sc, offreg) & (WI_OFF_BUSY|WI_OFF_ERR)))

sys/dev/ic/if_wi.c

1332

if (CSR_READ_2(sc, WI_DATA0) != 0x1234 ||

sys/dev/ic/if_wi.c

1333

CSR_READ_2(sc, WI_DATA0) != 0x5678)

sys/dev/ic/if_wi.c

1356

if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_ALLOC)

sys/dev/ic/if_wi.c

1363

*id = CSR_READ_2(sc, WI_ALLOC_FID);

sys/dev/ic/if_wi.c

3023

power = CSR_READ_2(sc, WI_RESP0);

sys/dev/ic/if_wi.c

474

status = CSR_READ_2(sc, WI_EVENT_STAT);

sys/dev/ic/if_wi.c

489

id = CSR_READ_2(sc, WI_ALLOC_FID);

sys/dev/ic/if_wi.c

524

return CSR_READ_2(sc, fid);

sys/dev/ic/if_wi.c

904

t = CSR_READ_2(sc, WI_DATA1);

sys/dev/ic/if_wi.c

926

if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))

sys/dev/ic/if_wi.c

946

s = CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD;

sys/dev/ic/if_wi.c

949

s = CSR_READ_2(sc, WI_STATUS);

sys/dev/ic/mtd8xx.c

254

return (phy ? 0 : (int)CSR_READ_2(MTD_PHYCSR + (reg << 1)));

sys/dev/ic/re.c

1550

status = CSR_READ_2(sc, RL_ISR);

sys/dev/ic/re.c

477

rval = CSR_READ_2(sc, re8139_reg);

sys/dev/ic/rtl81x9.c

1277

return (CSR_READ_2(sc, rl8139_reg));

sys/dev/ic/rtl81x9.c

347

ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;

sys/dev/ic/rtl81x9.c

369

if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)

sys/dev/ic/rtl81x9.c

569

cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;

sys/dev/ic/rtl81x9.c

572

limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;

sys/dev/ic/rtl81x9.c

757

status = CSR_READ_2(sc, RL_ISR);

sys/dev/ic/rtl81x9reg.h

981

CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))

sys/dev/ic/rtl81x9reg.h

984

CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))

sys/dev/ic/xl.c

1425

while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {

sys/dev/ic/xl.c

2093

status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);

sys/dev/ic/xl.c

2219

status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);

sys/dev/ic/xl.c

224

if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))

sys/dev/ic/xl.c

2416

n = CSR_READ_2(sc, 12);

sys/dev/ic/xl.c

243

CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))

sys/dev/ic/xl.c

2469

sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);

sys/dev/ic/xl.c

247

CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))

sys/dev/ic/xl.c

341

ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;

sys/dev/ic/xl.c

359

if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)

sys/dev/ic/xl.c

490

if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)

sys/dev/ic/xl.c

537

word = CSR_READ_2(sc, XL_W0_EE_DATA);

sys/dev/ic/xl.c

677

mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);

sys/dev/ic/xl.c

778

if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))

sys/dev/ic/xl.c

800

CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,

sys/dev/isa/if_ex.c

485

i = CSR_READ_2(sc, IO_PORT_REG);

sys/dev/isa/if_ex.c

497

CSR_READ_2(sc, IO_PORT_REG);

sys/dev/isa/if_ex.c

619

if (!(CSR_READ_2(sc, IO_PORT_REG) & Done_bit))

sys/dev/isa/if_ex.c

621

tx_status = CSR_READ_2(sc, IO_PORT_REG);

sys/dev/isa/if_ex.c

622

sc->tx_head = CSR_READ_2(sc, IO_PORT_REG);

sys/dev/isa/if_ex.c

652

while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) {

sys/dev/isa/if_ex.c

653

rx_status = CSR_READ_2(sc, IO_PORT_REG);

sys/dev/isa/if_ex.c

654

sc->rx_head = CSR_READ_2(sc, IO_PORT_REG);

sys/dev/isa/if_ex.c

655

QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG);

sys/dev/isa/if_ex.c

838

CSR_READ_2(sc, IO_PORT_REG);

sys/dev/pci/if_alc.c

1338

burst = CSR_READ_2(sc, base + PCI_PCIE_DCSR);

sys/dev/pci/if_alc.c

2271

prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX);

sys/dev/pci/if_alc.c

754

CSR_READ_2(sc, ALC_GPHY_CFG);

sys/dev/pci/if_alc.c

759

CSR_READ_2(sc, ALC_GPHY_CFG);

sys/dev/pci/if_alc.c

985

linkcfg = CSR_READ_2(sc, sc->alc_expcap + PCI_PCIE_LCSR);

sys/dev/pci/if_ale.c

1298

prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);

sys/dev/pci/if_msk.c

353

return CSR_READ_2(sc, reg);

sys/dev/pci/if_msk.c

824

CSR_READ_2(sc, SK_LINK_CTRL)));

sys/dev/pci/if_se.c

448

rxfilt = CSR_READ_2(sc, RxMacControl);

sys/dev/pci/if_sk.c

211

return CSR_READ_2(sc, reg);

sys/dev/pci/if_sk.c

784

DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));

sys/dev/pci/if_sk.c

786

CSR_READ_2(sc, SK_LINK_CTRL)));

sys/dev/pci/if_ste.c

119

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)

sys/dev/pci/if_ste.c

122

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)

sys/dev/pci/if_ste.c

235

ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;

sys/dev/pci/if_ste.c

257

if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)

sys/dev/pci/if_ste.c

368

fcur = CSR_READ_2(sc, STE_MACCTL0) & STE_MACCTL0_FULLDUPLEX;

sys/dev/pci/if_ste.c

446

if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)

sys/dev/pci/if_ste.c

479

word = CSR_READ_2(sc, STE_EEPROM_DATA);

sys/dev/pci/if_ste.c

555

if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))

sys/dev/pci/if_ste.c

559

status = CSR_READ_2(sc, STE_ISR_ACK);

sys/dev/pci/if_stge.c

1027

(u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors);

sys/dev/pci/if_stge.c

1037

(u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) +

sys/dev/pci/if_stge.c

1038

(u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal);

sys/dev/pci/if_stge.c

1261

CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);

sys/dev/pci/if_stge.c

1265

CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);

sys/dev/pci/if_stge.c

1269

CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);

sys/dev/pci/if_stge.c

1386

if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)

sys/dev/pci/if_stge.c

1410

*data = CSR_READ_2(sc, STGE_EepromData);

sys/dev/pci/if_stge.c

301

sc->sc_arpcom.ac_enaddr[0] = CSR_READ_2(sc,

sys/dev/pci/if_stge.c

303

sc->sc_arpcom.ac_enaddr[1] = CSR_READ_2(sc,

sys/dev/pci/if_stge.c

305

sc->sc_arpcom.ac_enaddr[2] = CSR_READ_2(sc,

sys/dev/pci/if_stge.c

307

sc->sc_arpcom.ac_enaddr[3] = CSR_READ_2(sc,

sys/dev/pci/if_stge.c

309

sc->sc_arpcom.ac_enaddr[4] = CSR_READ_2(sc,

sys/dev/pci/if_stge.c

311

sc->sc_arpcom.ac_enaddr[5] = CSR_READ_2(sc,

sys/dev/pci/if_stge.c

714

if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0)

sys/dev/pci/if_stge.c

718

isr = CSR_READ_2(sc, STGE_IntStatusAck);

sys/dev/pci/if_tl.c

1245

ints = CSR_READ_2(sc, TL_HOST_INT);

sys/dev/pci/if_tl.c

302

return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));

sys/dev/pci/if_tl.c

361

f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));

sys/dev/pci/if_tl.c

372

f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));

sys/dev/pci/if_vge.c

209

word = CSR_READ_2(sc, VGE_EERDDAT);

sys/dev/pci/if_vge.c

328

rval = CSR_READ_2(sc, VGE_MIIDATA);

sys/dev/pci/if_vgevar.h

116

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))

sys/dev/pci/if_vgevar.h

123

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))

sys/dev/pci/if_vr.c

1096

status = CSR_READ_2(sc, VR_ISR);

sys/dev/pci/if_vr.c

1610

if (!(CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)))

sys/dev/pci/if_vr.c

187

CSR_READ_2(sc, reg) | (x))

sys/dev/pci/if_vr.c

191

CSR_READ_2(sc, reg) & ~(x))

sys/dev/pci/if_vr.c

233

frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);

sys/dev/pci/if_vr.c

392

if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON))

sys/dev/pci/if_vr.c

407

if (!(CSR_READ_2(sc, VR_COMMAND) &

sys/dev/pci/if_vr.c

429

if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))

sys/dev/pci/if_vr.c

953

i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);

sys/dev/pci/if_vr.c

998

i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);

sys/dev/pci/if_vte.c

1086

mdcsc = CSR_READ_2(sc, VTE_MDCSC);

sys/dev/pci/if_vte.c

1087

mcr = CSR_READ_2(sc, VTE_MCR1);

sys/dev/pci/if_vte.c

1091

if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0)

sys/dev/pci/if_vte.c

123

if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0)

sys/dev/pci/if_vte.c

1260

CSR_READ_2(sc, VTE_MISR);

sys/dev/pci/if_vte.c

1298

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

1304

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

1323

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

1328

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

133

return (CSR_READ_2(sc, VTE_MMRD));

sys/dev/pci/if_vte.c

1440

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

147

if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)

sys/dev/pci/if_vte.c

1495

CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

258

mid = CSR_READ_2(sc, VTE_MID0L);

sys/dev/pci/if_vte.c

261

mid = CSR_READ_2(sc, VTE_MID0M);

sys/dev/pci/if_vte.c

264

mid = CSR_READ_2(sc, VTE_MID0H);

sys/dev/pci/if_vte.c

766

mcr = CSR_READ_2(sc, VTE_MCR0);

sys/dev/pci/if_vte.c

791

CSR_READ_2(sc, VTE_CNT_RX_DONE);

sys/dev/pci/if_vte.c

792

CSR_READ_2(sc, VTE_CNT_MECNT0);

sys/dev/pci/if_vte.c

793

CSR_READ_2(sc, VTE_CNT_MECNT1);

sys/dev/pci/if_vte.c

794

CSR_READ_2(sc, VTE_CNT_MECNT2);

sys/dev/pci/if_vte.c

795

CSR_READ_2(sc, VTE_CNT_MECNT3);

sys/dev/pci/if_vte.c

796

CSR_READ_2(sc, VTE_CNT_TX_DONE);

sys/dev/pci/if_vte.c

797

CSR_READ_2(sc, VTE_CNT_MECNT4);

sys/dev/pci/if_vte.c

798

CSR_READ_2(sc, VTE_CNT_PAUSE);

sys/dev/pci/if_vte.c

810

CSR_READ_2(sc, VTE_MECISR);

sys/dev/pci/if_vte.c

812

stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE);

sys/dev/pci/if_vte.c

813

value = CSR_READ_2(sc, VTE_CNT_MECNT0);

sys/dev/pci/if_vte.c

816

value = CSR_READ_2(sc, VTE_CNT_MECNT1);

sys/dev/pci/if_vte.c

819

value = CSR_READ_2(sc, VTE_CNT_MECNT2);

sys/dev/pci/if_vte.c

821

value = CSR_READ_2(sc, VTE_CNT_MECNT3);

sys/dev/pci/if_vte.c

826

stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE);

sys/dev/pci/if_vte.c

827

value = CSR_READ_2(sc, VTE_CNT_MECNT4);

sys/dev/pci/if_vte.c

831

value = CSR_READ_2(sc, VTE_CNT_PAUSE);

sys/dev/pci/if_vte.c

852

status = CSR_READ_2(sc, VTE_MISR);

sys/dev/pci/if_vte.c

872

status = CSR_READ_2(sc, VTE_MISR);

sys/dev/pci/if_wi_pci.c

411

if (CSR_READ_2(sc, WI_SW0) != WI_DRVR_MAGIC) {