Symbol: CSR_READ_1
sys/dev/ic/acx.c
1474
*val = CSR_READ_1(sc, ACXREG_EEPROM_DATA);
sys/dev/ic/acx.c
1501
*val = CSR_READ_1(sc, ACXREG_PHY_DATA);
sys/dev/ic/re.c
1054
CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
sys/dev/ic/re.c
1056
CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
sys/dev/ic/re.c
2014
CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
sys/dev/ic/re.c
213
CSR_READ_1(sc, RL_EECMD) | x)
sys/dev/ic/re.c
2152
if ((CSR_READ_1(sc, sc->rl_txstart) &
sys/dev/ic/re.c
217
CSR_READ_1(sc, RL_EECMD) & ~x)
sys/dev/ic/re.c
2315
CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) |
sys/dev/ic/re.c
2322
CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
sys/dev/ic/re.c
2326
CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
sys/dev/ic/re.c
2375
if ((CSR_READ_1(sc, sc->rl_cfg1) & RL_CFG1_PME) == 0) {
sys/dev/ic/re.c
2380
if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_AUXPWR) == 0)
sys/dev/ic/re.c
2392
val = CSR_READ_1(sc, sc->rl_cfg5);
sys/dev/ic/re.c
2397
val = CSR_READ_1(sc, sc->rl_cfg3);
sys/dev/ic/re.c
2402
val = CSR_READ_1(sc, sc->rl_cfg5);
sys/dev/ic/re.c
2407
val = CSR_READ_1(sc, sc->rl_cfg3);
sys/dev/ic/re.c
2490
command = CSR_READ_1(sc, RL_COMMAND);
sys/dev/ic/re.c
2503
CSR_READ_1(sc, RL_COMMAND);
sys/dev/ic/re.c
329
if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
sys/dev/ic/re.c
375
rval = CSR_READ_1(sc, RL_GMEDIASTAT);
sys/dev/ic/re.c
469
rval = CSR_READ_1(sc, RL_MEDIASTAT);
sys/dev/ic/re.c
646
if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
sys/dev/ic/re.c
838
cfg2 = CSR_READ_1(sc, sc->rl_cfg2);
sys/dev/ic/re.c
865
eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
sys/dev/ic/rtl81x9.c
1271
return (CSR_READ_1(sc, RL_MEDIASTAT));
sys/dev/ic/rtl81x9.c
155
CSR_READ_1(sc, RL_EECMD) | x)
sys/dev/ic/rtl81x9.c
159
CSR_READ_1(sc, RL_EECMD) & ~x)
sys/dev/ic/rtl81x9.c
214
if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
sys/dev/ic/rtl81x9.c
254
CSR_READ_1(sc, RL_MII) | x)
sys/dev/ic/rtl81x9.c
258
CSR_READ_1(sc, RL_MII) & ~x)
sys/dev/ic/rtl81x9.c
499
if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
sys/dev/ic/rtl81x9.c
579
while ((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
sys/dev/ic/rtl81x9reg.h
975
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
sys/dev/ic/rtl81x9reg.h
978
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
sys/dev/ic/xl.c
1352
while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
sys/dev/ic/xl.c
1492
*p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
sys/dev/ic/xl.c
1507
CSR_READ_1(sc, XL_W4_BADSSD);
sys/dev/ic/xl.c
1987
macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
sys/dev/ic/xl.c
2108
if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
sys/dev/ic/xl.c
2117
if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
sys/dev/ic/xl.c
477
(CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
sys/dev/ic/xl.c
570
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
sys/dev/ic/xl.c
609
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
sys/dev/ic/xl.c
744
(CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
sys/dev/isa/if_ex.c
157
if (((count1 = CSR_READ_1(sc, ID_REG)) & Id_Mask) != Id_Sig)
sys/dev/isa/if_ex.c
159
count2 = CSR_READ_1(sc, ID_REG);
sys/dev/isa/if_ex.c
160
count2 = CSR_READ_1(sc, ID_REG);
sys/dev/isa/if_ex.c
161
count2 = CSR_READ_1(sc, ID_REG);
sys/dev/isa/if_ex.c
302
temp_reg = CSR_READ_1(sc, EEPROM_REG);
sys/dev/isa/if_ex.c
314
CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md |
sys/dev/isa/if_ex.c
316
CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins |
sys/dev/isa/if_ex.c
318
CSR_WRITE_1(sc, REG3, (CSR_READ_1(sc, REG3) & 0x3f));
sys/dev/isa/if_ex.c
320
CSR_WRITE_1(sc, INT_NO_REG, (CSR_READ_1(sc, INT_NO_REG) & 0xf8) |
sys/dev/isa/if_ex.c
342
CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT);
sys/dev/isa/if_ex.c
542
CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT);
sys/dev/isa/if_ex.c
575
while ((int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) {
sys/dev/isa/if_ex.c
687
CSR_READ_1(sc, IO_PORT_REG);
sys/dev/isa/if_ex.c
801
CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode);
sys/dev/isa/if_ex.c
802
CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
sys/dev/isa/if_ex.c
808
CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Multi_IA);
sys/dev/isa/if_ex.c
809
CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
sys/dev/isa/if_ex.c
847
if ((CSR_READ_1(sc, STATUS_REG) & Exec_Int) == 0)
sys/dev/isa/if_ex.c
850
status = CSR_READ_1(sc, CMD_REG);
sys/dev/isa/if_ex.c
859
CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) & 0xDE);
sys/dev/isa/if_ex.c
861
CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
sys/dev/isa/if_ex.c
905
current = CSR_READ_1(sc, REG3);
sys/dev/isa/if_ex.c
962
data = (data << 1) | ((CSR_READ_1(sc, EEPROM_REG) & EEDO) ? 1 : 0);
sys/dev/pci/if_ipw.c
113
return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA);
sys/dev/pci/if_ipw.c
2044
*datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3));
sys/dev/pci/if_iwi.c
118
return CSR_READ_1(sc, IWI_CSR_INDIRECT_DATA);
sys/dev/pci/if_lge.c
604
if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
sys/dev/pci/if_lge.c
771
txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
sys/dev/pci/if_lge.c
949
if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
sys/dev/pci/if_msk.c
359
return CSR_READ_1(sc, reg);
sys/dev/pci/if_msk.c
822
DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
sys/dev/pci/if_re_pci.c
193
cfg = CSR_READ_1(sc, RL_CFG2);
sys/dev/pci/if_sk.c
217
return CSR_READ_1(sc, reg);
sys/dev/pci/if_ste.c
125
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
sys/dev/pci/if_ste.c
128
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
sys/dev/pci/if_ste.c
500
rxmode = CSR_READ_1(sc, STE_RX_MODE);
sys/dev/pci/if_ste.c
703
while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
sys/dev/pci/if_ste.c
772
ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
sys/dev/pci/if_ste.c
773
+ CSR_READ_1(sc, STE_MULTI_COLLS)
sys/dev/pci/if_ste.c
774
+ CSR_READ_1(sc, STE_SINGLE_COLLS);
sys/dev/pci/if_stge.c
1579
return (CSR_READ_1(sc, STGE_PhyCtrl));
sys/dev/pci/if_stge.c
331
sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
sys/dev/pci/if_tl.c
295
return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
sys/dev/pci/if_tl.c
339
f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
sys/dev/pci/if_tl.c
350
f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
sys/dev/pci/if_vge.c
198
if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
sys/dev/pci/if_vge.c
240
dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
sys/dev/pci/if_vge.c
253
if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
sys/dev/pci/if_vge.c
273
if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
sys/dev/pci/if_vge.c
290
if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
sys/dev/pci/if_vge.c
305
if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
sys/dev/pci/if_vge.c
321
if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
sys/dev/pci/if_vge.c
342
if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
sys/dev/pci/if_vge.c
360
if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
sys/dev/pci/if_vge.c
427
if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
sys/dev/pci/if_vge.c
473
rxctl = CSR_READ_1(sc, VGE_RXCTL);
sys/dev/pci/if_vge.c
528
if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
sys/dev/pci/if_vge.c
544
if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
sys/dev/pci/if_vgevar.h
114
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
sys/dev/pci/if_vgevar.h
121
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
sys/dev/pci/if_vr.c
179
CSR_READ_1(sc, reg) | (x))
sys/dev/pci/if_vr.c
183
CSR_READ_1(sc, reg) & ~(x))
sys/dev/pci/if_vr.c
203
CSR_READ_1(sc, VR_MIICMD) | (x))
sys/dev/pci/if_vr.c
207
CSR_READ_1(sc, VR_MIICMD) & ~(x))
sys/dev/pci/if_vr.c
220
CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
sys/dev/pci/if_vr.c
228
if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
sys/dev/pci/if_vr.c
251
CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
sys/dev/pci/if_vr.c
261
if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
sys/dev/pci/if_vr.c
338
rxfilt = CSR_READ_1(sc, VR_RXCFG);
sys/dev/pci/if_vr.c
591
sc->arpcom.ac_enaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);