sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

490

config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

491

config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

492

config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

493

config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

494

dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

579

struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

602

pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

603

pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

604

pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

635

pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

636

pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

637

pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

662

struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

663

&cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

680

pipe_data->mode = VBLANK;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

681

pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

682

pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

684

pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

685

pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

686

pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

687

pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

688

pipe_data->pipe_config.vblank_data.vblank_end =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

693

populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

722

struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

745

pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

747

pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

753

pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

755

pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

782

struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

783

&cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

794

pipe_data->mode = SUBVP;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

795

pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

796

pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

797

pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

798

pipe_data->pipe_config.subvp_data.main_vblank_start =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

800

pipe_data->pipe_config.subvp_data.main_vblank_end =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

802

pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

803

pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

804

pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

818

pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

819

pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

822

pipe_data->pipe_config.subvp_data.prefetch_lines =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

826

pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

829

pipe_data->pipe_config.subvp_data.processing_delay_lines =

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

834

pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

836

pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

838

pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

847

pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

849

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

851

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

853

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1945

struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5672

struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];

usr.bin/less/lsystem.c

171

return (pipe_data(cmd, tpos, bpos));

usr.bin/less/lsystem.c

173

return (pipe_data(cmd, mpos, bpos));

usr.bin/less/lsystem.c

175

return (pipe_data(cmd, tpos, bpos));

usr.bin/less/lsystem.c

177

return (pipe_data(cmd, tpos, mpos));

usr.bin/less/lsystem.c

25

static int pipe_data(char *cmd, off_t spos, off_t epos);