Symbol: pg_cntl
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1862
struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1895
if (pg_cntl != NULL)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1896
pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
118
if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1184
struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1186
if (!pg_cntl)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
119
if (dc->res_pool->pg_cntl->funcs->print_pg_status)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1192
if (pg_cntl->funcs->hpo_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1193
pg_cntl->funcs->hpo_pg_control(pg_cntl, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
120
dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1200
if (pg_cntl->funcs->hubp_dpp_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1201
pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1207
if (pg_cntl->funcs->dsc_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1208
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1214
if (pg_cntl->funcs->dsc_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1215
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1220
if (pg_cntl->funcs->hubp_dpp_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1221
pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1227
if (pg_cntl->funcs->plane_otg_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1228
pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1261
struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1263
if (!pg_cntl)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1269
if (pg_cntl->funcs->plane_otg_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1270
pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1275
if (pg_cntl->funcs->dsc_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1276
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1283
if (pg_cntl->funcs->hubp_dpp_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1284
pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1289
if (pg_cntl->funcs->dsc_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1290
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1295
if (pg_cntl->funcs->hpo_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1296
pg_cntl->funcs->hpo_pg_control(pg_cntl, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1303
struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1305
if (!pg_cntl)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
320
if (dc->res_pool->pg_cntl) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
321
if (dc->res_pool->pg_cntl->funcs->init_pg_status)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
322
dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
625
struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
768
if (pg_cntl != NULL) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
769
if (pg_cntl->funcs->dsc_pg_control != NULL) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
809
pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
103
struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
105
if (!pg_cntl || dc->debug.ignore_pg)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
110
if (pg_cntl->funcs->dsc_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
111
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
116
if (pg_cntl->funcs->hubp_dpp_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
117
pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
124
if (pg_cntl->funcs->plane_otg_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
125
pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
156
struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
158
if (!pg_cntl || dc->debug.ignore_pg)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
165
if (pg_cntl->funcs->plane_otg_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
166
pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
173
if (pg_cntl->funcs->hubp_dpp_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
174
pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
178
if (pg_cntl->funcs->dsc_pg_control)
sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
179
pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
315
struct pg_cntl *pg_cntl;
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
40
void (*dsc_pg_control)(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
41
void (*hubp_dpp_pg_control)(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
42
void (*hpo_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
43
void (*io_clk_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
44
void (*plane_otg_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
45
void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
46
void (*opp_pg_control)(struct pg_cntl *pg_cntl, unsigned int opp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
47
void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
48
void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
49
void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
50
void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
51
void (*init_pg_status)(struct pg_cntl *pg_cntl);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
52
void (*print_pg_status)(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
142
pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
145
static bool pg_cntl35_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
147
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
175
void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
177
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
182
bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
183
pg_cntl->ctx->dc->debug.disable_hubp_power_gate ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
184
pg_cntl->ctx->dc->debug.disable_dpp_power_gate ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
185
pg_cntl->ctx->dc->idle_optimizations_allowed;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
190
block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
233
pg_cntl->pg_pipe_res_enable[PG_HUBP][hubp_dpp_inst] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
234
pg_cntl->pg_pipe_res_enable[PG_DPP][hubp_dpp_inst] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
238
static bool pg_cntl35_hpo_pg_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
240
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
249
void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
251
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
258
if (pg_cntl->ctx->dc->debug.ignore_pg ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
259
pg_cntl->ctx->dc->debug.disable_hpo_power_gate ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
260
pg_cntl->ctx->dc->idle_optimizations_allowed)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
263
block_enabled = pg_cntl35_hpo_pg_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
283
pg_cntl->pg_res_enable[PG_HPO] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
286
static bool pg_cntl35_io_clk_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
288
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
297
void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
299
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
306
if (pg_cntl->ctx->dc->debug.ignore_pg ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
307
pg_cntl->ctx->dc->idle_optimizations_allowed)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
310
block_enabled = pg_cntl35_io_clk_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
32
#define TO_DCN_PG_CNTL(pg_cntl)\
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
33
container_of(pg_cntl, struct dcn_pg_cntl, base)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
331
pg_cntl->pg_res_enable[PG_DCCG] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
332
pg_cntl->pg_res_enable[PG_DIO] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
333
pg_cntl->pg_res_enable[PG_DCIO] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
336
static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
338
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
347
void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
350
if (pg_cntl->ctx->dc->idle_optimizations_allowed)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
354
pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
357
void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
360
if (pg_cntl->ctx->dc->idle_optimizations_allowed)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
364
pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
367
void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
370
if (pg_cntl->ctx->dc->idle_optimizations_allowed)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
374
pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
377
void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
379
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
388
if (pg_cntl->ctx->dc->debug.ignore_pg ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
389
pg_cntl->ctx->dc->debug.disable_optc_power_gate ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
390
pg_cntl->ctx->dc->idle_optimizations_allowed)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
393
block_enabled = pg_cntl35_plane_otg_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
402
for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
403
struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
410
if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i])
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
413
if (pg_cntl->pg_pipe_res_enable[PG_OPP][i])
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
416
if (pg_cntl->pg_pipe_res_enable[PG_OPTC][i])
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
422
|| !all_stream_disabled || pg_cntl->pg_res_enable[PG_DWB])
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
434
for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
435
pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
436
pg_cntl->pg_pipe_res_enable[PG_OPP][i] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
437
pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
439
pg_cntl->pg_res_enable[PG_DWB] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
442
void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
444
if (pg_cntl->ctx->dc->idle_optimizations_allowed)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
447
pg_cntl->pg_res_enable[PG_DWB] = power_on;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
45
pg_cntl->ctx->logger
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
450
static bool pg_cntl35_mem_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
452
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
461
void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
466
pg_cntl->pg_res_enable[PG_HPO] = pg_cntl35_hpo_pg_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
468
block_enabled = pg_cntl35_io_clk_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
469
pg_cntl->pg_res_enable[PG_DCCG] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
47
static bool pg_cntl35_dsc_pg_status(struct pg_cntl *pg_cntl, unsigned int dsc_inst)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
470
pg_cntl->pg_res_enable[PG_DIO] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
471
pg_cntl->pg_res_enable[PG_DCIO] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
473
block_enabled = pg_cntl35_mem_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
474
pg_cntl->pg_res_enable[PG_DCHUBBUB] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
475
pg_cntl->pg_res_enable[PG_DCHVM] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
477
for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
478
block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
479
pg_cntl->pg_pipe_res_enable[PG_HUBP][i] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
480
pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
482
block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
483
pg_cntl->pg_pipe_res_enable[PG_DSC][i] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
486
block_enabled = pg_cntl35_plane_otg_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
487
for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
488
pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
489
pg_cntl->pg_pipe_res_enable[PG_OPP][i] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
49
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
490
pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
492
pg_cntl->pg_res_enable[PG_DWB] = block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
495
static void pg_cntl35_print_pg_status(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
504
block_enabled = pg_cntl35_io_clk_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
507
block_enabled = pg_cntl35_mem_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
510
block_enabled = pg_cntl35_plane_otg_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
513
block_enabled = pg_cntl35_hpo_pg_status(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
516
for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
517
block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
52
if (pg_cntl->ctx->dc->debug.ignore_pg)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
520
block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
539
struct pg_cntl *pg_cntl35_create(
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
546
struct pg_cntl *base;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
567
void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
569
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(*pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
572
*pg_cntl = NULL;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
76
void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
78
struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
83
bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
84
pg_cntl->ctx->dc->debug.disable_dsc_power_gate ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
85
pg_cntl->ctx->dc->idle_optimizations_allowed;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
90
block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, dsc_inst);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
166
struct pg_cntl base;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
172
void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
173
void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
175
void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
176
void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
177
void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
178
void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
180
void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
182
void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
184
void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
185
void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
187
struct pg_cntl *pg_cntl35_create(
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
193
void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1559
if (pool->base.pg_cntl != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1560
dcn_pg_cntl_destroy(&pool->base.pg_cntl);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2014
pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2015
if (pool->base.pg_cntl == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1539
if (pool->base.pg_cntl != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1540
dcn_pg_cntl_destroy(&pool->base.pg_cntl);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1986
pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1987
if (pool->base.pg_cntl == NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1540
if (pool->base.pg_cntl != NULL)
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1541
dcn_pg_cntl_destroy(&pool->base.pg_cntl);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1987
pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1988
if (pool->base.pg_cntl == NULL) {