sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1830

r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status);

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

664

pci_read_config_dword(us_pdev, aer_cap + PCI_ERR_COR_STATUS,

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

666

pci_read_config_dword(us_pdev, aer_cap + PCI_ERR_UNCOR_STATUS,

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

671

pci_read_config_dword(us_pdev, PCI_PRIMARY_BUS,

sys/dev/pci/drm/amd/amdgpu/vi.c

1157

pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1);

sys/dev/pci/drm/amd/amdgpu/vi.c

1181

pci_read_config_dword(adev->pdev, LINK_CAP, &data);

sys/dev/pci/drm/i915/display/intel_opregion.c

899

pci_read_config_dword(pdev, ASLS, &asls);

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

123

pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);

sys/dev/pci/drm/i915/intel_gvt.c

119

pci_read_config_dword(pdev, i, mem + i);

sys/dev/pci/drm/i915/soc/intel_gmch.c

125

pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);

sys/dev/pci/drm/i915/soc/intel_gmch.c

128

pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);

sys/dev/pci/drm/i915/soc/intel_gmch.c

146

pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);

sys/dev/pci/drm/i915/soc/intel_gmch.c

157

pci_read_config_dword(i915->gmch.pdev, DEVEN,

sys/dev/pci/drm/i915/soc/intel_gmch.c

165

pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915),

sys/dev/pci/drm/i915/soc/intel_gmch.c

71

pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi);

sys/dev/pci/drm/i915/soc/intel_gmch.c

72

pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo);