op_mode
if (done || !wr_trail || force_one_volume || op_mode == OP_TAR)
if (op_mode == OP_PAX)
else if (op_mode == OP_CPIO)
extern enum op_mode { OP_PAX, OP_TAR, OP_CPIO } op_mode;
if (op_mode == OP_TAR && Lflag) {
if (arcn->type == PAX_DIR && op_mode != OP_CPIO) {
if (op_mode == OP_PAX || errno != EPERM || vflag ||
if (op_mode == OP_PAX || errno != EPERM || vflag ||
op_mode = OP_TAR;
op_mode = OP_CPIO;
op_mode = OP_PAX;
enum op_mode op_mode; /* what program are we acting as? */
ar5k_ar5210_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
hal->ah_op_mode = op_mode;
ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
hal->ah_op_mode = op_mode;
ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
hal->ah_op_mode = op_mode;
prop.op_mode = MFI_PR_OPMODE_MANUAL;
prop.op_mode = MFI_PR_OPMODE_DISABLED;
prop.op_mode = MFI_PR_OPMODE_AUTO;
switch (prop.op_mode) {
DEVNAME(sc), prop.op_mode);
uint8_t op_mode;
u_int32_t rs_status, op_mode;
op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE);
if (ISSET(op_mode, C_CH_ENABLE))
if (was_activated && dm->secure_display_ctx.op_mode == LEGACY_MODE) {
if (dm->secure_display_ctx.op_mode == LEGACY_MODE &&
if (adev->dm.secure_display_ctx.op_mode == LEGACY_MODE)
else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE)
if (adev->dm.secure_display_ctx.op_mode == LEGACY_MODE)
else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE)
adev->dm.secure_display_ctx.op_mode = DISPLAY_CRC_MODE;
enum secure_display_mode op_mode;
prop.op_mode = MFI_PR_OPMODE_MANUAL;
prop.op_mode = MFI_PR_OPMODE_DISABLED;
prop.op_mode = MFI_PR_OPMODE_AUTO;
switch (prop.op_mode) {
DEVNAME(sc), prop.op_mode);
unsigned int op_mode = dwc2_op_mode(hsotg);
return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
(op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
(op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
unsigned int op_mode = dwc2_op_mode(hsotg);
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
unsigned int op_mode = dwc2_op_mode(hsotg);
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
unsigned op_mode:3;
switch (hsotg->hw_params.op_mode) {
u32 op_mode = hsotg->hw_params.op_mode;
op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
switch (hsotg->hw_params.op_mode) {
if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
switch (hsotg->hw_params.op_mode) {
hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>