sys/arch/octeon/dev/cn30xxfau.c

70

octeon_xkphys_write_8(addr, value);

sys/arch/octeon/dev/cn30xxfpavar.h

90

octeon_xkphys_write_8(ptr, (dwbcount & 0x0ffULL));

sys/arch/octeon/dev/cn30xxpkovar.h

145

octeon_xkphys_write_8(addr, value);

sys/arch/octeon/dev/cn30xxpowvar.h

184

octeon_xkphys_write_8(ptr, args);

sys/arch/octeon/dev/cn30xxuart.c

178

octeon_xkphys_write_8(MIO_UART0_LCR, lcr | LCR_DLAB);

sys/arch/octeon/dev/cn30xxuart.c

181

octeon_xkphys_write_8(MIO_UART0_LCR, lcr);

sys/arch/octeon/dev/cn30xxuart.c

230

octeon_xkphys_write_8(MIO_UART0_RBR, (uint8_t)c);

sys/arch/octeon/dev/if_cnmac.c

1199

octeon_xkphys_write_8(PIP_GBL_CFG, reg);

sys/arch/octeon/dev/if_ogx.c

2177

octeon_xkphys_write_8(op, addr);

sys/arch/octeon/dev/octmmc.c

350

octeon_xkphys_write_8(MIO_BOOT_CFG, 0);

sys/arch/octeon/dev/octpcie.c

465

octeon_xkphys_write_8(rst_reg, val);

sys/arch/octeon/dev/octpcie.c

471

octeon_xkphys_write_8(rst_reg, val);

sys/arch/octeon/dev/octrng.c

100

octeon_xkphys_write_8(OCTRNG_CONTROL_ADDR, control_reg);

sys/arch/octeon/dev/octrtc.c

205

octeon_xkphys_write_8(MIO_TWS_SW_TWSI, twsi.reg);

sys/arch/octeon/dev/octrtc.c

297

octeon_xkphys_write_8(MIO_TWS_SW_TWSI_EXT, 0);

sys/arch/octeon/dev/octrtc.c

298

octeon_xkphys_write_8(MIO_TWS_SW_TWSI, twsi.reg);

sys/arch/octeon/octeon/machdep.c

989

octeon_xkphys_write_8(RST_SOFT_RST, 1);

sys/arch/octeon/octeon/machdep.c

991

octeon_xkphys_write_8(OCTEON_CIU_BASE +