sys/arch/octeon/dev/cn30xxfau.c

57

return octeon_xkphys_read_8(addr);

sys/arch/octeon/dev/cn30xxfpavar.h

66

return octeon_xkphys_read_8(addr);

sys/arch/octeon/dev/cn30xxgmx.c

464

qlm_cfg = octeon_xkphys_read_8(MIO_QLM_CFG(2));

sys/arch/octeon/dev/cn30xxgmx.c

466

qlm_cfg = octeon_xkphys_read_8(MIO_QLM_CFG(0));

sys/arch/octeon/dev/cn30xxpowvar.h

97

return octeon_xkphys_read_8(ptr);

sys/arch/octeon/dev/cn30xxuart.c

177

lcr = octeon_xkphys_read_8(MIO_UART0_LCR);

sys/arch/octeon/dev/cn30xxuart.c

179

divisor = octeon_xkphys_read_8(MIO_UART0_DLL) |

sys/arch/octeon/dev/cn30xxuart.c

180

octeon_xkphys_read_8(MIO_UART0_DLH) << 8;

sys/arch/octeon/dev/cn30xxuart.c

202

while (((octeon_xkphys_read_8(MIO_UART0_LSR) & LSR_TXRDY) == 0) &&

sys/arch/octeon/dev/cn30xxuart.c

203

((octeon_xkphys_read_8(MIO_UART0_USR) & USR_TXFIFO_NOTFULL) == 0))

sys/arch/octeon/dev/cn30xxuart.c

242

while ((octeon_xkphys_read_8(MIO_UART0_LSR) & LSR_RXRDY) == 0)

sys/arch/octeon/dev/cn30xxuart.c

245

c = (uint8_t)octeon_xkphys_read_8(MIO_UART0_RBR);

sys/arch/octeon/dev/if_cnmac.c

1196

reg = octeon_xkphys_read_8(PIP_GBL_CFG);

sys/arch/octeon/dev/if_ogx.c

2163

return octeon_xkphys_read_8(op);

sys/arch/octeon/dev/if_ogx.c

829

(void)octeon_xkphys_read_8(op);

sys/arch/octeon/dev/if_ogx.c

867

(void)octeon_xkphys_read_8(op);

sys/arch/octeon/dev/if_ogx.c

964

resp = octeon_xkphys_read_8(op);

sys/arch/octeon/dev/octpcie.c

464

val = octeon_xkphys_read_8(rst_reg);

sys/arch/octeon/dev/octpcie.c

466

(void)octeon_xkphys_read_8(rst_reg);

sys/arch/octeon/dev/octpcie.c

472

(void)octeon_xkphys_read_8(rst_reg);

sys/arch/octeon/dev/octpcie.c

477

val = octeon_xkphys_read_8(ctl_reg);

sys/arch/octeon/dev/octpcie.c

679

if ((octeon_xkphys_read_8(MIO_RST_CTL(port->port_index)) &

sys/arch/octeon/dev/octpcie.c

684

if ((octeon_xkphys_read_8(RST_CTL(port->port_index)) &

sys/arch/octeon/dev/octrng.c

98

control_reg = octeon_xkphys_read_8(OCTRNG_CONTROL_ADDR);

sys/arch/octeon/dev/octrtc.c

209

twsi.reg = octeon_xkphys_read_8(MIO_TWS_SW_TWSI);

sys/arch/octeon/dev/octrtc.c

301

twsi.reg = octeon_xkphys_read_8(MIO_TWS_SW_TWSI);

sys/arch/octeon/octeon/machdep.c

1066

return octeon_xkphys_read_8(reg);

sys/arch/octeon/octeon/machdep.c

691

mio_rst_boot = octeon_xkphys_read_8(MIO_RST_BOOT);

sys/arch/octeon/octeon/machdep.c

695

rst_boot = octeon_xkphys_read_8(RST_BOOT);

sys/arch/octeon/octeon/machdep.c

756

val = octeon_xkphys_read_8(MIO_RST_BOOT);

sys/arch/octeon/octeon/machdep.c

763

val = octeon_xkphys_read_8(RST_BOOT);

sys/arch/octeon/octeon/machdep.c

812

core_mask = octeon_xkphys_read_8(OCTEON_CIU3_BASE + CIU3_FUSE);

sys/arch/octeon/octeon/machdep.c

815

core_mask = octeon_xkphys_read_8(OCTEON_CIU_BASE + CIU_FUSE);