out32rb
out32rb(addr + reg, val);
#define DBDMA_ST4_ENDIAN(a, x) out32rb(a, x)
#define dbdma_st32(a,x) out32rb((a),(x))
out32rb(sc->sc_reg + I2S_WORDSIZE, 0x02000200);
out32rb(sc->sc_reg + I2S_INT, I2S_INT_CLKSTOPPEND);
out32rb(sc->sc_reg + I2S_FORMAT, reg);
out32rb(heathrow_FCR, v);
out32rb(heathrow_FCR, v);
out32rb(heathrow_FCR, v);
out32rb(heathrow_FCR, v);
out32rb(heathrow_FCR, v);
out32rb(&dmareg->d_cmdptrhi, 0);
out32rb(&dmareg->d_cmdptrlo, sc->sc_txdbdma->d_paddr);
out32rb(fcr2, x);
out32rb(fcr2, x);
out32rb(keywest + 0x1c000, 0);
out32rb(keywest + 0x1a3e0, 0x41);
out32rb(fcr2, x);
out32rb(fcr2, x);
out32rb(INT_ENABLE_REG1,
out32rb(INT_ENABLE_REG0, macintr_ienable_l[macintr_pri_share[ipl]]);
out32rb(INT_CLEAR_REG0, state0);
out32rb(INT_CLEAR_REG1, state1);
out32rb(sc->sc_fcr, fcr);
out32rb(sc->sc_fcr, fcr);
out32rb(sc->sc_fcr, fcr);
out32rb(sc->sc_fcr, fcr);
out32rb(sc->sc_fcr, fcr);
out32rb(addr, val);
out32rb(sc->sc_reg + I2S_INT, I2S_INT_CLKSTOPPEND);
out32rb(sc->sc_reg + I2S_FORMAT, CLKSRC_VS);
out32rb(sc->obiomem + offset, bits);
out32rb(sc->obiomem + offset, bits);
out32rb(sc->obiomem + 0x40, val);