Symbol: optimization_phase_params
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
206
static bool dml2_top_optimization_perform_optimization_phase(struct dml2_optimization_phase_locals *l, const struct optimization_phase_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
282
static bool dml2_top_optimization_perform_optimization_phase_1(struct dml2_optimization_phase_locals *l, const struct optimization_phase_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
795
struct optimization_phase_params mcache_phase = {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
872
memset(&l->min_clock_for_latency_phase, 0, sizeof(struct optimization_phase_params));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
889
memset(&l->mcache_phase, 0, sizeof(struct optimization_phase_params));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
915
memset(&l->uclk_pstate_phase, 0, sizeof(struct optimization_phase_params));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
934
memset(&l->vmin_phase, 0, sizeof(struct optimization_phase_params));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
962
memset(&l->stutter_phase, 0, sizeof(struct optimization_phase_params));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
913
struct optimization_phase_params min_clock_for_latency_phase;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
914
struct optimization_phase_params mcache_phase;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
915
struct optimization_phase_params uclk_pstate_phase;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
916
struct optimization_phase_params vmin_phase;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
917
struct optimization_phase_params stutter_phase;