lib/libcrypto/asn1/asn1_par.c

123

const unsigned char *p, *ep, *tot, *op, *opp;

lib/libcrypto/asn1/asn1_par.c

226

opp = op;

lib/libcrypto/asn1/asn1_par.c

227

if (d2i_ASN1_OBJECT(&o, &opp, len + hl) !=

lib/libcrypto/asn1/asn1_par.c

250

opp = op;

lib/libcrypto/asn1/asn1_par.c

251

os = d2i_ASN1_OCTET_STRING(NULL, &opp, len + hl);

lib/libcrypto/asn1/asn1_par.c

253

opp = os->data;

lib/libcrypto/asn1/asn1_par.c

257

if (((opp[i] < ' ') &&

lib/libcrypto/asn1/asn1_par.c

258

(opp[i] != '\n') &&

lib/libcrypto/asn1/asn1_par.c

259

(opp[i] != '\r') &&

lib/libcrypto/asn1/asn1_par.c

260

(opp[i] != '\t')) ||

lib/libcrypto/asn1/asn1_par.c

261

(opp[i] > '~')) {

lib/libcrypto/asn1/asn1_par.c

270

if (BIO_write(bp, (const char *)opp,

lib/libcrypto/asn1/asn1_par.c

280

"%02X", opp[i]) <= 0)

lib/libcrypto/asn1/asn1_par.c

290

(const char *)opp,

lib/libcrypto/asn1/asn1_par.c

303

opp = op;

lib/libcrypto/asn1/asn1_par.c

304

ai = d2i_ASN1_INTEGER(NULL, &opp, len + hl);

lib/libcrypto/asn1/asn1_par.c

329

opp = op;

lib/libcrypto/asn1/asn1_par.c

330

ae = d2i_ASN1_ENUMERATED(NULL, &opp, len + hl);

sbin/disklabel/editor.c

1577

struct partition opp, *pp = &lp->d_partitions[partno];

sbin/disklabel/editor.c

1596

opp = *pp;

sbin/disklabel/editor.c

1603

*pp = opp;

sbin/disklabel/editor.c

1613

struct partition opp, *pp = &lp->d_partitions[partno];

sbin/disklabel/editor.c

1626

opp = *pp;

sbin/disklabel/editor.c

1634

*pp = opp;

sbin/disklabel/editor.c

1644

struct partition opp, *pp = &lp->d_partitions[partno];

sbin/disklabel/editor.c

1673

opp = *pp;

sbin/disklabel/editor.c

1682

*pp = opp;

sbin/disklabel/editor.c

872

struct partition opp, *pp;

sbin/disklabel/editor.c

879

opp = *pp;

sbin/disklabel/editor.c

889

*pp = opp;

sys/arch/arm/arm/cpu.c

347

uint32_t opp;

sys/arch/arm/arm/cpu.c

429

opp = OF_getpropint(ci->ci_node, "operating-points-v2", 0);

sys/arch/arm/arm/cpu.c

430

if (opp)

sys/arch/arm/arm/cpu.c

431

cpu_opp_init(ci, opp);

sys/arch/arm/arm/cpu.c

606

struct opp *ot_opp;

sys/arch/arm/arm/cpu.c

647

ot->ot_opp = mallocarray(count, sizeof(struct opp),

sys/arch/arm/arm/cpu.c

726

ot->ot_opp = mallocarray(count, sizeof(struct opp),

sys/arch/arm64/arm64/cpu.c

1527

uint32_t opp;

sys/arch/arm64/arm64/cpu.c

1673

opp = OF_getpropint(ci->ci_node, "operating-points-v2", 0);

sys/arch/arm64/arm64/cpu.c

1674

if (opp) {

sys/arch/arm64/arm64/cpu.c

1675

cpu_opp_init(ci, opp);

sys/arch/arm64/arm64/cpu.c

2216

ot->ot_opp = mallocarray(count, sizeof(struct opp),

sys/arch/arm64/arm64/cpu.c

289

struct opp *ot_opp;

sys/arch/arm64/dev/aplcpu.c

240

ot->ot_opp = mallocarray(count, sizeof(struct opp),

sys/arch/arm64/dev/aplcpu.c

56

struct opp *ot_opp;

sys/arch/riscv64/riscv64/cpu.c

249

uint32_t opp;

sys/arch/riscv64/riscv64/cpu.c

327

opp = OF_getpropint(ci->ci_node, "operating-points-v2", 0);

sys/arch/riscv64/riscv64/cpu.c

328

if (opp)

sys/arch/riscv64/riscv64/cpu.c

329

cpu_opp_init(ci, opp);

sys/arch/riscv64/riscv64/cpu.c

626

struct opp *ot_opp;

sys/arch/riscv64/riscv64/cpu.c

679

ot->ot_opp = mallocarray(count, sizeof(struct opp),

sys/dev/pci/drm/amd/display/dc/core/dc.c

1673

if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1675

pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1720

if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1722

pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3637

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3641

odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/core/dc.c

810

pipe_ctx->stream_res.opp->dyn_expansion = option;

sys/dev/pci/drm/amd/display/dc/core/dc.c

811

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/core/dc.c

812

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/core/dc.c

857

pipes->stream_res.opp->funcs->

sys/dev/pci/drm/amd/display/dc/core/dc.c

858

opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);

sys/dev/pci/drm/amd/display/dc/core/dc.c

897

pipes->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1162

hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

863

block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

870

block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2196

struct output_pixel_processor *opp = opp_head->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2202

if (opp && opp->funcs->opp_get_left_edge_extra_pixel_count)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2204

opp->funcs->opp_get_left_edge_extra_pixel_count(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2205

opp, pipe_ctx->stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2273

if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2316

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2323

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2324

pipe->stream_res.opp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2332

pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2338

pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2545

split_pipe->stream_res.opp = pool->opps[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3696

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3715

pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3724

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3841

pipe_ctx->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3849

pipe_ctx->stream_res.opp = pool->opps[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5469

sec_pipe->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5471

sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5474

dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/dc.h

798

bool opp : 1; /* Output pixel processing */

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

533

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

536

struct dce110_opp *opp110 = TO_DCE110_OPP(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

545

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

548

struct dce110_opp *opp110 = TO_DCE110_OPP(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

557

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

560

struct dce110_opp *opp110 = TO_DCE110_OPP(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

568

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

571

struct dce110_opp *opp110 = TO_DCE110_OPP(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

578

static void program_formatter_420_memory(struct output_pixel_processor *opp)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

580

struct dce110_opp *opp110 = TO_DCE110_OPP(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

598

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

603

struct dce110_opp *opp110 = TO_DCE110_OPP(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

637

static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

639

struct dce110_opp *opp110 = TO_DCE110_OPP(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

651

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

659

program_formatter_420_memory(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

662

opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

666

opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

670

program_formatter_reset_dig_resync_fifo(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

677

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

685

program_formatter_420_memory(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

688

opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

692

opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

696

program_formatter_reset_dig_resync_fifo(opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

762

void dce110_opp_destroy(struct output_pixel_processor **opp)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

764

if (*opp)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

765

kfree(FROM_DCE11_OPP(*opp));

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

766

*opp = NULL;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

304

#define TO_DCE110_OPP(opp)\

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

305

container_of(opp, struct dce110_opp, base)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

32

#define FROM_DCE11_OPP(opp)\

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

33

container_of(opp, struct dce110_opp, base)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

330

void dce110_opp_destroy(struct output_pixel_processor **opp);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

336

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

340

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

344

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

350

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

347

if (pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

348

copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.h

30

#define TO_DCN201_OPP(opp)\

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.h

31

container_of(opp, struct dcn201_opp, base)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1913

sec_pipe->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1915

sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1625

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1626

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1630

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1631

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1637

odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1638

odm_pipe->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1643

odm_pipe->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1644

odm_pipe->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1235

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1236

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1450

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1452

mpc_tree_params = &(opp->mpc_tree_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1463

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1533

if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1534

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1535

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1682

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2253

inst_flags.opp_inst = pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2261

pipe->stream_res.opp->inst, lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2480

struct output_pixel_processor *opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2487

opp = grouped_pipes[i]->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2496

if (opp->funcs->opp_program_dpg_dimensions)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2497

opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2530

opp = grouped_pipes[i]->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2533

if (opp->funcs->opp_program_dpg_dimensions)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2534

opp->funcs->opp_program_dpg_dimensions(opp, width, height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2546

struct output_pixel_processor *opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2558

opp = grouped_pipes[i]->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2567

if (opp->funcs->opp_program_dpg_dimensions)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2568

opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2611

opp = grouped_pipes[i]->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2614

if (opp->funcs->opp_program_dpg_dimensions)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2615

opp->funcs->opp_program_dpg_dimensions(opp, width, height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2750

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2751

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2895

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2961

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3108

pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3530

pipe_ctx->stream_res.opp->funcs->opp_program_stereo(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3531

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3567

if (!pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3571

if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3577

pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1033

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1195

int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1200

opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1327

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1328

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1590

if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1601

|| old_pipe->stream_res.opp != new_pipe->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2005

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2006

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2011

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2012

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2027

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2580

struct output_pixel_processor *opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2584

if (!opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2588

if (!opp->funcs->dpg_is_pending(opp))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2599

return opp->funcs->dpg_is_blanked(opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2941

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3013

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3209

pipe_ctx->stream_res.opp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3216

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3259

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

412

struct output_pixel_processor *opp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

433

opp = dc->res_pool->opps[opp_id_src0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

436

if (opp->funcs->dpg_is_blanked && opp->funcs->dpg_is_blanked(opp))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

449

opp->funcs->opp_set_disp_pattern_generator(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

450

opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

471

hws->funcs.wait_for_blank_complete(opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

871

opp_inst[i] = opp_heads[i]->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

949

opp_heads[i]->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

950

opp_heads[i]->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

952

opp_heads[i]->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

953

opp_heads[i]->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

139

struct output_pixel_processor *opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

171

struct output_pixel_processor *opp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

187

opp = dc->res_pool->opps[opp_id_src0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

189

opp->funcs->opp_set_disp_pattern_generator(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

190

opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

199

hws->funcs.wait_for_blank_complete(opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

319

pipe_ctx->stream_res.opp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

324

pipe_ctx->stream_res.opp = res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

385

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

388

mpc_tree_params = &(opp->mpc_tree_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

411

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

431

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

521

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1183

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

259

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

343

if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

360

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

396

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

113

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

119

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

160

opp_instances[0] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

165

opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

204

odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

205

odm_pipe->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

434

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

441

opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1070

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1080

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1119

opp_instances[0] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1124

opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1151

odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1152

odm_pipe->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1154

odm_pipe->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1155

odm_pipe->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1279

int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1286

opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1638

struct output_pixel_processor *opp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1663

opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1683

if (opp && opp->funcs->opp_set_disp_pattern_generator)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1684

opp->funcs->opp_set_disp_pattern_generator(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1685

opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1709

if (opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1710

hws->funcs.wait_for_blank_complete(opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1768

if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

445

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

481

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

554

if (pipe_ctx->stream_res.opp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

555

pipe_ctx->stream_res.opp->ctx &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

567

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1059

if (j == PG_OPP && new_pipe->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1060

update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1083

cur_pipe->stream_res.opp != new_pipe->stream_res.opp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1084

new_pipe->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1085

update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

369

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

375

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

416

opp_instances[0] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

421

opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

460

odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

461

odm_pipe->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

734

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

831

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

832

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

961

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

981

if (pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

982

update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1576

opp_inst[i] = opp_heads[i]->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1588

opp_heads[i]->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1589

opp_heads[i]->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1591

opp_heads[i]->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1592

opp_heads[i]->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2059

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2060

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2065

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2066

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2081

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2559

if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2570

|| old_pipe->stream_res.opp != new_pipe->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

616

struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

669

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

737

opp_inst[i] = opp_heads[i]->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

843

opp_heads[i]->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

844

opp_heads[i]->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

846

opp_heads[i]->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

847

opp_heads[i]->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

852

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

853

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

864

hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

92

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

152

bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

347

struct output_pixel_processor *opp;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

306

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

311

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

317

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

322

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

326

void (*opp_destroy)(struct output_pixel_processor **opp);

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

329

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

334

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

338

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

348

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

353

struct output_pixel_processor *opp);

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

355

bool (*dpg_is_pending)(struct output_pixel_processor *opp);

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

359

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

363

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

368

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

489

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

509

opp->funcs->opp_program_bit_depth_reduction(opp, &params);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

526

odm_opp = odm_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

548

opp->funcs->opp_program_bit_depth_reduction(opp, &params);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

558

odm_opp = odm_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

848

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

855

odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

140

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

143

struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

248

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

253

struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

259

if (opp->dyn_expansion == DYN_EXPANSION_DISABLE)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

291

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

294

struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

301

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

305

struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

313

opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

317

opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

324

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

328

struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

367

void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

369

struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

379

void opp1_destroy(struct output_pixel_processor **opp)

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

381

kfree(TO_DCN10_OPP(*opp));

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

382

*opp = NULL;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

168

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

174

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

179

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

183

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

187

void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

189

void opp1_destroy(struct output_pixel_processor **opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

30

#define TO_DCN10_OPP(opp)\

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

31

container_of(opp, struct dcn10_opp, base)

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

278

opp2_dpg_set_blank_color(opp, solid_color);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

295

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

298

struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

306

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

309

struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

324

bool opp2_dpg_is_blanked(struct output_pixel_processor *opp)

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

326

struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

341

bool opp2_dpg_is_pending(struct output_pixel_processor *opp)

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

343

struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

355

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

359

struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

360

uint32_t count = opp2_get_left_edge_extra_pixel_count(opp, pixel_encoding, is_primary);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

369

uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

373

!opp->ctx->dc->debug.force_chroma_subsampling_1tap &&

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

43

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

52

struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

147

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

157

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

160

bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

162

bool opp2_dpg_is_pending(struct output_pixel_processor *opp);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

165

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

169

struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

172

uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

30

#define TO_DCN20_OPP(opp)\

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

31

container_of(opp, struct dcn20_opp, base)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

663

struct dce110_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

666

if (!opp)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

669

dce110_opp_construct(opp,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

671

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1141

pipe_ctx->stream_res.opp = pool->opps[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

707

struct dce110_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

710

if (!opp)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

713

dce110_opp_construct(opp,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

715

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

683

struct dce110_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

686

if (!opp)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

689

dce110_opp_construct(opp,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

691

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

430

struct dce110_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

433

if (!opp)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

436

dce110_opp_construct(opp,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

438

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

514

struct dce110_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

517

if (!opp)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

520

dce60_opp_construct(opp,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

522

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

520

struct dce110_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

523

if (!opp)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

526

dce110_opp_construct(opp,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

528

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1100

idle_pipe->stream_res.opp = head_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

604

struct dcn10_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

607

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

612

dcn10_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

614

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1520

next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1522

next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2162

sec_dpp_pipe->stream_res.opp = opp_head->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

770

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

773

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

778

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

780

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1019

idle_pipe->stream_res.opp = head_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

664

struct dcn201_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

667

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

671

dcn201_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

673

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1028

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1031

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1036

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1038

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1558

sec_pipe->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1560

sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

770

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

773

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

778

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

780

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

733

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

736

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

741

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

743

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

574

struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

576

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

581

dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

582

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

549

struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

551

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

556

dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

557

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

936

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

939

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

944

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

946

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

972

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

975

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

980

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

982

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

934

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

937

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

942

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

944

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

928

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

931

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

936

dcn20_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

938

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2761

idle_pipe->stream_res.opp = head_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2820

free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2852

free_pipe->stream_res.opp = pool->opps[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

840

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

843

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

855

dcn35_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

858

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

860

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

820

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

823

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

835

dcn35_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

838

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

840

return &opp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

821

struct dcn20_opp *opp =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

824

if (!opp) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

836

dcn35_opp_construct(opp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

839

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

841

return &opp->base;

sys/kern/subr_disk.c

868

struct partition *opp, *npp;

sys/kern/subr_disk.c

890

opp = &olp->d_partitions[i];

sys/kern/subr_disk.c

893

(DL_GETPOFFSET(npp) != DL_GETPOFFSET(opp) ||

sys/kern/subr_disk.c

894

DL_GETPSIZE(npp) < DL_GETPSIZE(opp)))

sys/kern/subr_disk.c

900

if (npp->p_fstype == FS_UNUSED && opp->p_fstype != FS_UNUSED) {

sys/kern/subr_disk.c

901

npp->p_fragblock = opp->p_fragblock;

sys/kern/subr_disk.c

902

npp->p_cpg = opp->p_cpg;

usr.sbin/tcpdump/print-icmp6.c

521

const struct nd_opt_prefix_info *opp;

usr.sbin/tcpdump/print-icmp6.c

592

opp = (struct nd_opt_prefix_info *)op;

usr.sbin/tcpdump/print-icmp6.c

593

TCHECK(opp->nd_opt_pi_prefix);

usr.sbin/tcpdump/print-icmp6.c

595

if (opp->nd_opt_pi_flags_reserved & ND_OPT_PI_FLAG_ONLINK)

usr.sbin/tcpdump/print-icmp6.c

597

if (opp->nd_opt_pi_flags_reserved & ND_OPT_PI_FLAG_AUTO)

usr.sbin/tcpdump/print-icmp6.c

599

if (opp->nd_opt_pi_flags_reserved)

usr.sbin/tcpdump/print-icmp6.c

602

if ((u_int32_t)ntohl(opp->nd_opt_pi_valid_time) == ~0U)

usr.sbin/tcpdump/print-icmp6.c

605

printf("%u", (u_int32_t)ntohl(opp->nd_opt_pi_valid_time));

usr.sbin/tcpdump/print-icmp6.c

609

if ((u_int32_t)ntohl(opp->nd_opt_pi_preferred_time) == ~0U)

usr.sbin/tcpdump/print-icmp6.c

612

printf("%u", (u_int32_t)ntohl(opp->nd_opt_pi_preferred_time));

usr.sbin/tcpdump/print-icmp6.c

615

printf("prefix=%s/%d", ip6addr_string(&opp->nd_opt_pi_prefix),

usr.sbin/tcpdump/print-icmp6.c

616

opp->nd_opt_pi_prefix_len);

usr.sbin/tcpdump/print-icmp6.c

617

if (opp->nd_opt_pi_len != 4)