nxphdmi_write
int nxphdmi_write(struct nxphdmi_softc *, uint16_t, uint8_t);
nxphdmi_write(sc, TDA_PLL_SERIAL_1, 0x00);
nxphdmi_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
nxphdmi_write(sc, TDA_PLL_SERIAL_3, 0x00);
nxphdmi_write(sc, TDA_SERIALIZER, 0x00);
nxphdmi_write(sc, TDA_BUFFER_OUT, 0x00);
nxphdmi_write(sc, TDA_PLL_SCG1, 0x00);
nxphdmi_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
nxphdmi_write(sc, TDA_PLL_SCGN1, 0xfa);
nxphdmi_write(sc, TDA_PLL_SCGN2, 0x00);
nxphdmi_write(sc, TDA_PLL_SCGR1, 0x5b);
nxphdmi_write(sc, TDA_PLL_SCGR2, 0x00);
nxphdmi_write(sc, TDA_PLL_SCG2, 0x10);
nxphdmi_write(sc, TDA_MUX_VP_VIP_OUT, 0x24);
nxphdmi_write(sc, TDA_DDC_CTRL, DDC_ENABLE);
nxphdmi_write(sc, TDA_TX3, 39);
nxphdmi_write(sc, TDA_VIP_CNTRL_0, 0x23);
nxphdmi_write(sc, TDA_VIP_CNTRL_1, 0x01);
nxphdmi_write(sc, TDA_VIP_CNTRL_2, 0x45);
ret |= nxphdmi_write(sc, reg, buf);
ret |= nxphdmi_write(sc, reg, buf);
nxphdmi_write(sc, TDA_DDC_ADDR, 0xa0);
nxphdmi_write(sc, TDA_DDC_OFFS, 0x00);
nxphdmi_write(sc, TDA_DDC_SEGM_ADDR, 0x60);
nxphdmi_write(sc, TDA_DDC_SEGM, 0x00);
nxphdmi_write(sc, TDA_EDID_CTRL, 1);
nxphdmi_write(sc, TDA_EDID_CTRL, 0);
nxphdmi_write(sc, TDA_ENC_CNTRL, ENC_CNTRL_DVI_MODE);
nxphdmi_write(sc, TDA_HVF_CNTRL_0,
nxphdmi_write(sc, TDA_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
nxphdmi_write(sc, TDA_VIP_CNTRL_4,
nxphdmi_write(sc, TDA_SERIALIZER, 0);
nxphdmi_write(sc, TDA_HVF_CNTRL_1, HVF_CNTRL_1_VQR_FULL);
nxphdmi_write(sc, TDA_RPT_CNTRL, 0);
nxphdmi_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
nxphdmi_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
nxphdmi_write(sc, TDA_ANA_GENERAL, 0x09);
nxphdmi_write(sc, TDA_VIP_CNTRL_3, reg);
nxphdmi_write(sc, TDA_TBG_CNTRL_1, reg);
nxphdmi_write(sc, TDA_VIDFORMAT, 0x00);
nxphdmi_write(sc, TDA_ENABLE_SPACE, 0x00);