Symbol: number_of_planes_minus_one
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
175
float viewport_width[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
176
float htotal[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
177
float vtotal[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
178
float v_sync_plus_back_porch[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
179
float vactive[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
180
float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
181
float viewport_height[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
182
enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
183
float dcc_rate[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
184
enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
185
float lb_bit_per_pixel[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
186
enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
187
enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
188
enum dcn_bw_defs output_format[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
189
enum dcn_bw_defs output_deep_color[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
190
enum dcn_bw_defs output[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
191
float scaler_rec_out_width[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
192
float scaler_recout_height[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
193
float underscan_output[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
194
float interlace_output[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
195
float override_hta_ps[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
196
float override_vta_ps[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
197
float override_hta_pschroma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
198
float override_vta_pschroma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
199
float urgent_latency_support_us[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
200
float h_ratio[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
201
float v_ratio[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
202
float htaps[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
203
float vtaps[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
204
float hta_pschroma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
205
float vta_pschroma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
216
float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
221
float dpp_per_plane[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
222
float det_buffer_size_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
223
float det_buffer_size_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
224
float swath_height_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
225
float swath_height_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
234
float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
235
float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
236
float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
237
float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
238
float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
239
float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
240
float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
241
float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
242
float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
243
float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
244
float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
262
float prefetch_bw[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
263
float meta_pte_bytes_per_frame[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
264
float meta_row_bytes[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
265
float dpte_bytes_per_row[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
266
float prefetch_lines_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
267
float prefetch_lines_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
268
float max_num_sw_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
269
float max_num_sw_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
270
float line_times_for_prefetch[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
271
float lines_for_meta_pte_with_immediate_flip[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
272
float lines_for_meta_pte_without_immediate_flip[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
273
float lines_for_meta_and_dpte_row_with_immediate_flip[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
274
float lines_for_meta_and_dpte_row_without_immediate_flip[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
275
float min_dppclk_using_single_dpp[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
276
float swath_width_ysingle_dpp[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
277
float byte_per_pixel_in_dety[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
278
float byte_per_pixel_in_detc[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
279
float number_of_dpp_required_for_det_and_lb_size[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
280
float required_phyclk[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
281
float read256_block_height_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
282
float read256_block_width_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
283
float read256_block_height_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
284
float read256_block_width_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
285
float max_swath_height_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
286
float max_swath_height_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
287
float min_swath_height_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
288
float min_swath_height_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
289
float read_bandwidth[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
290
float write_bandwidth[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
291
float pscl_factor[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
292
float pscl_factor_chroma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
352
float v_update_offset[number_of_planes_minus_one + 1][2];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
354
float v_update_width[number_of_planes_minus_one + 1][2];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
355
float v_ready_offset[number_of_planes_minus_one + 1][2];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
360
float total_immediate_flip_bytes[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
383
float prefetch_bandwidth[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
384
float v_init_pre_fill_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
385
float v_init_pre_fill_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
386
float max_num_swath_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
387
float max_num_swath_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
388
float prefill_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
389
float prefill_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
390
float v_startup[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
391
enum dcn_bw_defs allow_dram_clock_change_during_vblank[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
392
float allow_dram_self_refresh_during_vblank[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
393
float v_ratio_prefetch_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
394
float v_ratio_prefetch_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
395
float destination_lines_for_prefetch[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
396
float destination_lines_to_request_vm_inv_blank[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
397
float destination_lines_to_request_row_in_vblank[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
398
float min_ttuv_blank[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
399
float byte_per_pixel_dety[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
400
float byte_per_pixel_detc[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
401
float swath_width_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
402
float lines_in_dety[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
403
float lines_in_dety_rounded_down_to_swath[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
404
float lines_in_detc[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
405
float lines_in_detc_rounded_down_to_swath[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
406
float full_det_buffering_time_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
407
float full_det_buffering_time_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
408
float active_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
409
float v_blank_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
410
float dcfclk_deep_sleep_per_plane[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
411
float read_bandwidth_plane_luma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
412
float read_bandwidth_plane_chroma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
413
float display_pipe_line_delivery_time_luma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
414
float display_pipe_line_delivery_time_chroma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
415
float display_pipe_line_delivery_time_luma_prefetch[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
416
float display_pipe_line_delivery_time_chroma_prefetch[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
417
float pixel_pte_bytes_per_row[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
418
float meta_pte_bytes_frame[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
419
float meta_row_byte[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
420
float prefetch_source_lines_y[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
421
float prefetch_source_lines_c[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
422
float pscl_throughput[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
423
float pscl_throughput_chroma[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
424
float output_bpphdmi[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
425
float output_bppdp4_lane_hbr[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
426
float output_bppdp4_lane_hbr2[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
427
float output_bppdp4_lane_hbr3[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
428
float max_vstartup_lines[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
507
float v_update_offset_pix[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
509
float v_update_width_pix[number_of_planes_minus_one + 1];
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
510
float v_ready_offset_pix[number_of_planes_minus_one + 1];