mwx_write
mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, 0);
mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, mask);
mwx_write(sc, MT_WFDMA0_HOST_INT_STA, intr);
mwx_write(sc, MT_MCU_CMD, intr_sw);
mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, mask);
mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, 0);
mwx_write(sc, MT_PCIE_MAC_INT_ENABLE, 0xff);
mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, 0);
mwx_write(sc, MT_PCIE_MAC_INT_ENABLE, 0);
mwx_write(sc, MT_PCIE_MAC_INT_ENABLE, 0xff);
mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, sc->sc_intr_mask);
mwx_write(sc, q->mq_regbase + MT_DMA_DESC_BASE, dmaaddr);
mwx_write(sc, q->mq_regbase + MT_DMA_RING_SIZE, q->mq_count);
mwx_write(sc, q->mq_regbase + MT_DMA_CPU_IDX, 0);
mwx_write(sc, q->mq_regbase + MT_DMA_DMA_IDX, 0);
mwx_write(sc, q->mq_regbase + MT_DMA_CPU_IDX, q->mq_prod);
mwx_write(sc, q->mq_regbase + MT_DMA_CPU_IDX, q->mq_prod);
mwx_write(sc, q->mq_regbase + MT_DMA_CPU_IDX, q->mq_prod);
mwx_write(sc, MT_WFDMA0_RX_RING0_EXT_CTRL, P(0x0, 0x4));
mwx_write(sc, MT_WFDMA0_RX_RING1_EXT_CTRL, P(0x40, 0x4));
mwx_write(sc, MT_WFDMA0_RX_RING2_EXT_CTRL, P(0x80, 0x4));
mwx_write(sc, MT_WFDMA0_RX_RING3_EXT_CTRL, P(0xc0, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING0_EXT_CTRL, P(0x100, 0x10));
mwx_write(sc, MT_WFDMA0_TX_RING1_EXT_CTRL, P(0x200, 0x10));
mwx_write(sc, MT_WFDMA0_TX_RING2_EXT_CTRL, P(0x300, 0x10));
mwx_write(sc, MT_WFDMA0_TX_RING3_EXT_CTRL, P(0x400, 0x10));
mwx_write(sc, MT_WFDMA0_TX_RING15_EXT_CTRL, P(0x500, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING16_EXT_CTRL, P(0x540, 0x4));
mwx_write(sc, MT_WFDMA0_RX_RING0_EXT_CTRL, P(0x0, 0x4));
mwx_write(sc, MT_WFDMA0_RX_RING2_EXT_CTRL, P(0x40, 0x4));
mwx_write(sc, MT_WFDMA0_RX_RING3_EXT_CTRL, P(0x80, 0x4));
mwx_write(sc, MT_WFDMA0_RX_RING4_EXT_CTRL, P(0xc0, 0x4));
mwx_write(sc, MT_WFDMA0_RX_RING5_EXT_CTRL, P(0x100, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING0_EXT_CTRL, P(0x140, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING1_EXT_CTRL, P(0x180, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING2_EXT_CTRL, P(0x1c0, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING3_EXT_CTRL, P(0x200, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING4_EXT_CTRL, P(0x240, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING5_EXT_CTRL, P(0x280, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING6_EXT_CTRL, P(0x2c0, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING16_EXT_CTRL, P(0x340, 0x4));
mwx_write(sc, MT_WFDMA0_TX_RING17_EXT_CTRL, P(0x380, 0x4));
mwx_write(sc, MT_WFDMA0_RST_DTX_PTR, ~0);
mwx_write(sc, MT_WFDMA0_RST_DRX_PTR, ~0);
mwx_write(sc, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, sc->sc_intr_mask);
mwx_write(sc, MT_PCIE_MAC_INT_ENABLE, 0xff);
mwx_write(sc, MT_CONN_ON_LPCTL, PCIE_LPCR_HOST_SET_OWN);
mwx_write(sc, MT_CONN_ON_LPCTL, PCIE_LPCR_HOST_CLR_OWN);
mwx_write(sc, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE);
mwx_write(sc, MT_TOP_LPCR_HOST_BAND0, MT_TOP_LPCR_HOST_DRV_OWN);
mwx_write(sc, MT_WTBL_ITDR0, rate_idx);
mwx_write(sc, MT_WTBL_ITDR1, MT_WTBL_SPE_IDX_SEL);
mwx_write(sc, MT_WTBL_ITCR, ctrl);
mwx_write(sc, MT_TMAC_CDTR(0), cck + reg_offset);
mwx_write(sc, MT_TMAC_ODTR(0), ofdm + reg_offset);
mwx_write(sc, MT_TMAC_ICR0(0),