mvpp2_write
mvpp2_write(sc->sc, MVPP2_ISR_RXQ_GROUP_INDEX_REG,
mvpp2_write(sc->sc, MVPP2_ISR_RXQ_SUB_GROUP_CONFIG_REG,
mvpp2_write(sc->sc, MVPP2_AGGR_TXQ_UPDATE_REG, used);
mvpp2_write(sc->sc, MVPP2_ISR_MISC_CAUSE_REG, 0);
mvpp2_write(sc->sc, MVPP2_ISR_RX_TX_CAUSE_REG(sc->sc_id),
mvpp2_write(sc->sc, MVPP22_BM_ADDR_HIGH_RLS_REG,
mvpp2_write(sc->sc, MVPP2_BM_VIRT_RLS_REG,
mvpp2_write(sc->sc, MVPP2_BM_PHY_RLS_REG(pool),
mvpp2_write(sc->sc, MVPP2_ISR_RX_TX_MASK_REG(sc->sc_id),
mvpp2_write(sc, MVPP2_AGGR_TXQ_DESC_ADDR_REG(txq->id),
mvpp2_write(sc, MVPP2_AGGR_TXQ_DESC_SIZE_REG(txq->id),
mvpp2_write(sc->sc, MVPP2_TXQ_NUM_REG, txq->id);
mvpp2_write(sc->sc, MVPP2_TXQ_DESC_ADDR_REG,
mvpp2_write(sc->sc, MVPP2_TXQ_DESC_SIZE_REG,
mvpp2_write(sc->sc, MVPP2_TXQ_INDEX_REG, 0);
mvpp2_write(sc->sc, MVPP2_TXQ_RSVD_CLR_REG,
mvpp2_write(sc->sc, MVPP2_TXQ_PENDING_REG, reg);
mvpp2_write(sc->sc, MVPP2_TXQ_PREF_BUF_REG,
mvpp2_write(sc->sc, MVPP2_TXP_SCHED_PORT_INDEX_REG,
mvpp2_write(sc->sc, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), reg);
mvpp2_write(sc->sc, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
mvpp2_write(sc->sc, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
mvpp2_write(sc->sc, MVPP2_RXQ_NUM_REG, rxq->id);
mvpp2_write(sc->sc, MVPP2_RXQ_DESC_ADDR_REG,
mvpp2_write(sc->sc, MVPP2_RXQ_DESC_SIZE_REG, MVPP2_NRXDESC);
mvpp2_write(sc->sc, MVPP2_RXQ_INDEX_REG, 0);
void mvpp2_write(struct mvpp2_softc *, bus_addr_t, uint32_t);
mvpp2_write(sc->sc, MVPP2_ISR_RX_TX_MASK_REG(sc->sc_id), 0);
mvpp2_write(sc->sc, MVPP2_TX_PORT_FLUSH_REG, reg);
mvpp2_write(sc->sc, MVPP2_TX_PORT_FLUSH_REG, reg);
mvpp2_write(sc->sc, MVPP2_TXQ_NUM_REG, txq->id);
mvpp2_write(sc->sc, MVPP2_TXQ_PREF_BUF_REG, reg);
mvpp2_write(sc->sc, MVPP2_TXQ_PREF_BUF_REG, reg);
mvpp2_write(sc->sc, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
mvpp2_write(sc->sc, MVPP2_TXQ_NUM_REG, txq->id);
mvpp2_write(sc->sc, MVPP2_TXQ_DESC_ADDR_REG, 0);
mvpp2_write(sc->sc, MVPP2_TXQ_DESC_SIZE_REG, 0);
mvpp2_write(sc->sc, MVPP22_BM_ADDR_HIGH_RLS_REG,
mvpp2_write(sc->sc, MVPP2_BM_VIRT_RLS_REG,
mvpp2_write(sc->sc, MVPP2_BM_PHY_RLS_REG(pool),
mvpp2_write(sc->sc, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
mvpp2_write(sc->sc, MVPP2_RXQ_NUM_REG, rxq->id);
mvpp2_write(sc->sc, MVPP2_RXQ_DESC_ADDR_REG, 0);
mvpp2_write(sc->sc, MVPP2_RXQ_DESC_SIZE_REG, 0);
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(prxq), val);
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(prxq), val);
mvpp2_write(port->sc, MVPP2_ISR_ENABLE_REG(port->sc_id),
mvpp2_write(port->sc, MVPP2_ISR_ENABLE_REG(port->sc_id),
mvpp2_write(port->sc, MVPP2_TXP_SCHED_PORT_INDEX_REG,
mvpp2_write(port->sc, MVPP2_TXP_SCHED_CMD_1_REG, 0);
mvpp2_write(port->sc, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
mvpp2_write(port->sc, MVPP2_TXP_SCHED_PERIOD_REG, port->sc->sc_tclk /
mvpp2_write(port->sc, MVPP2_TXP_SCHED_REFILL_REG, val);
mvpp2_write(port->sc, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
mvpp2_write(port->sc, MVPP2_RX_CTRL_REG(port->sc_id),
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(queue), val);
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(queue), val);
mvpp2_write(port->sc, MVPP2_TXP_SCHED_PORT_INDEX_REG,
mvpp2_write(port->sc, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
mvpp2_write(port->sc, MVPP2_TXP_SCHED_PORT_INDEX_REG,
mvpp2_write(port->sc, MVPP2_TXP_SCHED_Q_CMD_REG,
mvpp2_write(port->sc, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(prxq), val);
mvpp2_write(port->sc, MVPP2_TXP_SCHED_PORT_INDEX_REG,
mvpp2_write(port->sc, MVPP2_TXP_SCHED_MTU_REG, val);
mvpp2_write(port->sc, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
mvpp2_write(port->sc, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), val);
mvpp2_write(port->sc, MVPP2_RXQ_NUM_REG, rxq->id);
mvpp2_write(port->sc, MVPP2_RXQ_THRESH_REG, rxq->pkts_coal);
mvpp2_write(port->sc, MVPP2_TXQ_NUM_REG, txq->id);
mvpp2_write(port->sc, MVPP2_TXQ_THRESH_REG,
mvpp2_write(port->sc, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
mvpp2_write(port->sc, MVPP2_ISR_TX_THRESHOLD_REG(port->sc_id), val);
mvpp2_write(sc, MVPP2_PRS_TCAM_IDX_REG, pe->index);
mvpp2_write(sc, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
mvpp2_write(sc, MVPP2_PRS_SRAM_IDX_REG, pe->index);
mvpp2_write(sc, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
mvpp2_write(sc, MVPP2_PRS_TCAM_IDX_REG, pe->index);
mvpp2_write(sc, MVPP2_PRS_SRAM_IDX_REG, pe->index);
mvpp2_write(sc, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
mvpp2_write(sc, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
mvpp2_write(sc, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
mvpp2_write(sc, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
mvpp2_write(sc, MVPP2_CLS_LKP_INDEX_REG, val);
mvpp2_write(sc, MVPP2_CLS_LKP_TBL_REG, le->data);
mvpp2_write(sc, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
mvpp2_write(port->sc, MVPP2_CLS_PORT_WAY_REG, val);
mvpp2_write(port->sc, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->sc_id),
mvpp2_write(port->sc, MVPP2_CLS_SWFWD_P2HQ_REG(port->sc_id),
mvpp2_write(port->sc, MVPP2_CLS_SWFWD_PCTRL_REG, val);
mvpp2_write(sc, MVPP2_TX_SNOOP_REG, 0x1);
mvpp2_write(sc, MVPP22_BM_ADDR_HIGH_RLS_REG, 0);
mvpp2_write(sc, MVPP22_AXI_BM_WR_ATTR_REG, reg);
mvpp2_write(sc, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, reg);
mvpp2_write(sc, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, reg);
mvpp2_write(sc, MVPP22_AXI_RX_DATA_WR_ATTR_REG, reg);
mvpp2_write(sc, MVPP22_AXI_BM_RD_ATTR_REG, reg);
mvpp2_write(sc, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, reg);
mvpp2_write(sc, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, reg);
mvpp2_write(sc, MVPP22_AXI_TX_DATA_RD_ATTR_REG, reg);
mvpp2_write(sc, MVPP22_AXI_RD_NORMAL_CODE_REG, reg);
mvpp2_write(sc, MVPP22_AXI_WR_NORMAL_CODE_REG, reg);
mvpp2_write(sc, MVPP22_AXI_RD_SNOOP_CODE_REG, reg);
mvpp2_write(sc, MVPP22_AXI_WR_SNOOP_CODE_REG, reg);
mvpp2_write(sc, MVPP2_BM_INTR_MASK_REG(i), 0);
mvpp2_write(sc, MVPP2_BM_INTR_CAUSE_REG(i), 0);
mvpp2_write(sc, MVPP2_BM_POOL_CTRL_REG(i),
mvpp2_write(sc, MVPP2_BM_POOL_BASE_REG(i),
mvpp2_write(sc, MVPP22_BM_POOL_BASE_HIGH_REG,
mvpp2_write(sc, MVPP2_BM_POOL_SIZE_REG(i),
mvpp2_write(sc, MVPP2_BM_POOL_CTRL_REG(i),
mvpp2_write(sc, MVPP2_POOL_BUF_SIZE_REG(i),
mvpp2_write(sc, MVPP22_BM_ADDR_HIGH_RLS_REG,
mvpp2_write(sc, MVPP2_BM_VIRT_RLS_REG,
mvpp2_write(sc, MVPP2_BM_PHY_RLS_REG(i),
mvpp2_write(sc, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
mvpp2_write(sc, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
mvpp2_write(sc, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
mvpp2_write(sc, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
mvpp2_write(sc, MVPP2_RX_DATA_FIFO_SIZE_REG(i),
mvpp2_write(sc, MVPP2_RX_ATTR_FIFO_SIZE_REG(i),
mvpp2_write(sc, MVPP2_RX_MIN_PKT_SIZE_REG, MVPP2_RX_FIFO_PORT_MIN_PKT);
mvpp2_write(sc, MVPP2_RX_FIFO_INIT_REG, 0x1);
mvpp2_write(sc, MVPP22_TX_FIFO_SIZE_REG(0),
mvpp2_write(sc, MVPP22_TX_FIFO_THRESH_REG(0),
mvpp2_write(sc, MVPP22_TX_FIFO_SIZE_REG(i),
mvpp2_write(sc, MVPP22_TX_FIFO_THRESH_REG(i),
mvpp2_write(sc, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
mvpp2_write(sc, MVPP2_PRS_TCAM_IDX_REG, i);
mvpp2_write(sc, MVPP2_PRS_TCAM_DATA_REG(j), 0);
mvpp2_write(sc, MVPP2_PRS_SRAM_IDX_REG, i);
mvpp2_write(sc, MVPP2_PRS_SRAM_DATA_REG(j), 0);
mvpp2_write(sc, MVPP2_PRS_TCAM_IDX_REG, index);
mvpp2_write(sc, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
mvpp2_write(sc, MVPP2_PRS_INIT_LOOKUP_REG, reg);
mvpp2_write(sc, MVPP2_PRS_MAX_LOOP_REG(port), reg);
mvpp2_write(sc, MVPP2_PRS_INIT_OFFS_REG(port), reg);