mwx_set
mwx_set(sc, MT_WFDMA0_RST, MT_WFDMA0_RST_DMASHDL_ALL_RST |
mwx_set(sc, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS);
mwx_set(sc, MT_WFDMA0_GLO_CFG,
mwx_set(sc, MT_WFDMA0_GLO_CFG,
mwx_set(sc, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT);
mwx_set(sc, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
mwx_set(sc, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);
mwx_set(sc, MT_PCIE_MAC_PM, MT_PCIE_MAC_PM_L0S_DIS);
mwx_set(sc, MT_TMAC_CTCR0(band),
mwx_set(sc, MT_WF_RMAC_MIB_TIME0(band), MT_WF_RMAC_MIB_RXTIME_EN);
mwx_set(sc, MT_WF_RMAC_MIB_AIRTIME0(band), MT_WF_RMAC_MIB_RXTIME_EN);
mwx_set(sc, MT_MIB_SCR1(band), MT_MIB_TXDUR_EN);
mwx_set(sc, MT_MIB_SCR1(band), MT_MIB_RXDUR_EN);
mwx_set(sc, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
mwx_set(sc, MT_MDP_DCR0, MT_MDP_DCR0_RX_HDR_TRANS_EN);
mwx_set(sc, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
mwx_set(sc, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
mwx_set(sc, MT_ARB_SCR(0),
mwx_set(sc, MT_WF_RFCR(0), MT_WF_RFCR_DROP_OTHER_BEACON);
mwx_set(sc, MT_DMA_DCR0(0), MT_DMA_DCR0_RXD_G5_EN);