mvpp2_xlg_read
reg = mvpp2_xlg_read(sc, MV_XLG_INTERRUPT_MASK_REG);
reg = mvpp2_xlg_read(sc, MV_XLG_MAC_PORT_STATUS_REG);
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
reg = mvpp2_xlg_read(sc, MV_XLG_INTERRUPT_CAUSE_REG);
mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG) &
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL3_REG);
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL1_REG);
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
ctl0 = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
ctl4 = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL4_REG);
while ((mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG) &
uint32_t mvpp2_xlg_read(struct mvpp2_port *, bus_addr_t);
reg = mvpp2_xlg_read(sc, MV_XLG_EXTERNAL_INTERRUPT_MASK_REG);
reg = mvpp2_xlg_read(sc, MV_XLG_EXTERNAL_INTERRUPT_MASK_REG);
val = mvpp2_xlg_read(port, MV_XLG_PORT_MAC_CTRL0_REG);
val = mvpp2_xlg_read(port, MV_XLG_PORT_MAC_CTRL0_REG);