mvpp2_read
reg = mvpp2_read(sc->sc, MVPP2_ISR_RX_TX_CAUSE_REG(sc->sc_id));
nsent = (mvpp2_read(sc->sc, MVPP2_TXQ_SENT_REG(txq->id)) &
txq->prod = mvpp2_read(sc, MVPP2_AGGR_TXQ_INDEX_REG(txq->id));
reg = mvpp2_read(sc->sc, MVPP2_TXQ_PENDING_REG);
reg = mvpp2_read(sc->sc, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
mvpp2_read(sc->sc, MVPP2_TXQ_SENT_REG(txq->id));
uint32_t mvpp2_read(struct mvpp2_softc *, bus_addr_t);
reg = mvpp2_read(sc->sc, MVPP2_TX_PORT_FLUSH_REG);
reg = mvpp2_read(sc->sc, MVPP2_TXQ_PREF_BUF_REG);
pending = mvpp2_read(sc->sc, MVPP2_TXQ_PENDING_REG) &
mvpp2_read(sc->sc, MVPP2_TXQ_SENT_REG(txq->id));
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(prxq));
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(prxq));
val = mvpp2_read(port->sc, MVPP2_TXP_SCHED_REFILL_REG);
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(queue));
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(queue));
reg_data = (mvpp2_read(port->sc, MVPP2_TXP_SCHED_Q_CMD_REG)) &
reg_data = mvpp2_read(port->sc, MVPP2_TXP_SCHED_Q_CMD_REG);
uint32_t val = mvpp2_read(port->sc, MVPP2_RXQ_STATUS_REG(rxq_id));
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(prxq));
val = mvpp2_read(port->sc, MVPP2_TXP_SCHED_MTU_REG);
val = mvpp2_read(port->sc, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
val = mvpp2_read(port->sc, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
mvpp2_read(sc, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
mvpp2_read(sc, MVPP2_PRS_TCAM_DATA_REG(i));
mvpp2_read(sc, MVPP2_PRS_SRAM_DATA_REG(i));
val = mvpp2_read(port->sc, MVPP2_CLS_PORT_WAY_REG);
val = mvpp2_read(port->sc, MVPP2_CLS_SWFWD_PCTRL_REG);
mvpp2_read(sc, MVPP2_BM_POOL_CTRL_REG(i)) |
mvpp2_read(sc, MVPP2_BM_POOL_CTRL_REG(i)) |
inuse = mvpp2_read(sc, MVPP2_BM_POOL_PTRS_NUM_REG(i)) &
inuse += mvpp2_read(sc, MVPP2_BM_BPPI_PTRS_NUM_REG(i)) &
mvpp2_read(sc, MVPP2_BM_PHY_ALLOC_REG(i));
reg = mvpp2_read(sc, MVPP2_PRS_INIT_LOOKUP_REG);
reg = mvpp2_read(sc, MVPP2_PRS_MAX_LOOP_REG(port));
reg = mvpp2_read(sc, MVPP2_PRS_INIT_OFFS_REG(port));