mvpp2_gmac_read
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_MASK_REG);
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_MASK_REG);
reg = mvpp2_gmac_read(sc, MVPP2_PORT_STATUS0_REG);
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_CAUSE_REG);
mvpp2_gmac_read(sc, MVPP2_PORT_CTRL2_REG) |
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_CTRL_0_REG);
mvpp2_gmac_read(sc, MVPP2_PORT_CTRL2_REG) &
while (mvpp2_gmac_read(sc, MVPP2_PORT_CTRL2_REG) &
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
ctl0 = mvpp2_gmac_read(sc, MVPP2_PORT_CTRL0_REG);
ctl2 = mvpp2_gmac_read(sc, MVPP2_PORT_CTRL2_REG);
ctl4 = mvpp2_gmac_read(sc, MVPP2_PORT_CTRL4_REG);
panc = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
uint32_t mvpp2_gmac_read(struct mvpp2_port *, bus_addr_t);
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_SUM_MASK_REG);
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_SUM_MASK_REG);
val = mvpp2_gmac_read(port, MVPP2_GMAC_CTRL_0_REG);
val = mvpp2_gmac_read(port, MVPP2_GMAC_CTRL_0_REG);