sys/dev/pci/drm/i915/gvt/handlers.c

702

new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));

sys/dev/pci/drm/i915/i915_hwmon.c

112

return mul_u64_u32_shr(reg_value, scale_factor, nshift);

sys/dev/pci/drm/i915/i915_hwmon.c

161

*energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,

sys/dev/pci/drm/i915/i915_hwmon.c

192

out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);

sys/dev/pci/drm/i915/i915_hwmon.c

227

max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);

sys/dev/pci/drm/i915/i915_hwmon.c

431

min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);

sys/dev/pci/drm/i915/i915_hwmon.c

433

max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);

sys/dev/pci/drm/i915/i915_hwmon.c

520

*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

sys/dev/pci/drm/i915/i915_hwmon.c

637

*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),