sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6077

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6078

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6079

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2696

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2699

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2705

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2708

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2819

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2822

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2828

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2831

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2979

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2980

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2984

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2985

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3001

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3002

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3006

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3007

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3123

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3124

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3307

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3310

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3316

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3319

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3526

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3529

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3535

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3538

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6802

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6804

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6806

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6808

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6812

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6814

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6816

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6818

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2130

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2131

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2135

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2136

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2152

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2153

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2157

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2158

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2210

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2213

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2219

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2222

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2252

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2255

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2261

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2264

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2331

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2332

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5254

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5256

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5258

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5260

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5264

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5266

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5268

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5270

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4089

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4090

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4091

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4093

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4094

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4095

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3245

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3246

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3247

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3248

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3249

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3250

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3251

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3252

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3253

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3254

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3255

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3256

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

sys/dev/pci/drm/radeon/cik.c

3866

WREG32(CP_ME_CNTL, 0);

sys/dev/pci/drm/radeon/cik.c

3870

WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));

sys/dev/pci/drm/radeon/cik.c

4947

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);

sys/dev/pci/drm/radeon/cik.c

5151

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);

sys/dev/pci/drm/radeon/evergreen.c

3017

WREG32(CP_ME_CNTL, cp_me);

sys/dev/pci/drm/radeon/evergreen.c

3908

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);

sys/dev/pci/drm/radeon/evergreen.c

4018

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);

sys/dev/pci/drm/radeon/ni.c

1438

WREG32(CP_ME_CNTL, 0);

sys/dev/pci/drm/radeon/ni.c

1442

WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));

sys/dev/pci/drm/radeon/ni.c

1820

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);

sys/dev/pci/drm/radeon/rv770.c

1084

WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));

sys/dev/pci/drm/radeon/si.c

3443

WREG32(CP_ME_CNTL, 0);

sys/dev/pci/drm/radeon/si.c

3447

WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));

sys/dev/pci/drm/radeon/si.c

3860

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);

sys/dev/pci/drm/radeon/si.c

4029

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);