sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

341

WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

395

status = RREG32(mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

421

WREG32_P(mmUVD_STATUS, 0, ~(1<<2));

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

466

status = RREG32(mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

509

WREG32(mmUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

732

if (RREG32(mmUVD_STATUS) != 0)

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

220

if (RREG32(mmUVD_STATUS) != 0)

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

298

WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

353

status = RREG32(mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

379

WREG32_P(mmUVD_STATUS, 0, ~(1<<2));

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

424

status = RREG32(mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

467

WREG32(mmUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

213

if (RREG32(mmUVD_STATUS) != 0)

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

391

status = RREG32(mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

417

WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

479

WREG32(mmUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1176

(RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

539

if (RREG32(mmUVD_STATUS) != 0)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

808

status = RREG32(mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

835

WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

912

WREG32(mmUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1051

status = RREG32_SOC15(UVD, k, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1081

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

824

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

914

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

936

MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1021

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1171

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1196

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1231

WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1239

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1278

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1428

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1436

ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

292

RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

50

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

859

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

860

WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

931

status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

965

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

966

WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1019

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1020

WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1094

status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1125

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1175

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1211

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1230

r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1273

WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1281

RREG32_SOC15(VCN, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1383

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1391

ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1987

SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

328

RREG32_SOC15(VCN, 0, mmUVD_STATUS)))

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

59

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

996

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1157

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1186

tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1187

WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1261

status = RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1296

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1347

RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1435

SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1578

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1599

r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1637

WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1649

RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1961

ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1975

ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

527

RREG32_SOC15(VCN, i, mmUVD_STATUS)))

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

62

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1188

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1215

tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1216

WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1290

status = RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1322

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1380

RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1432

mmUVD_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1627

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1648

r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1693

WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1704

RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2223

ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2238

ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2260

if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

456

RREG32_SOC15(VCN, i, mmUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

66

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),