sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

384

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

386

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

388

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

405

WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

408

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

505

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

342

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

344

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

346

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

363

WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

366

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

463

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

344

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

375

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

385

WREG32(mmUVD_SOFT_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

401

WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

404

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

470

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

751

WREG32(mmUVD_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

791

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

801

WREG32(mmUVD_SOFT_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

903

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1031

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1044

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1061

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1065

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1158

WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

881

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

901

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

930

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

995

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1100

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1218

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1222

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1227

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

915

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

922

tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

925

WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

941

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

945

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1070

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1077

tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1080

WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1104

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1108

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1258

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1263

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1268

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

931

UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1233

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1236

WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1685

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1687

WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1688

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1690

WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);