sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5011

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5012

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5013

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5014

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5121

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5122

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5123

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5124

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5511

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5512

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5513

data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5514

data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4108

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4109

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4110

data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4111

data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6498

WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

499

uint32_t CP_INT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

481

uint32_t CP_INT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

490

uint32_t CP_INT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

501

uint32_t CP_INT_CNTL;

sys/dev/pci/drm/radeon/evergreen.c

4470

WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

sys/dev/pci/drm/radeon/evergreen.c

4565

WREG32(CP_INT_CNTL, cp_int_cntl);

sys/dev/pci/drm/radeon/ni.c

1370

WREG32(CP_INT_CNTL, cp_int_cntl);

sys/dev/pci/drm/radeon/r600.c

3622

WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

sys/dev/pci/drm/radeon/r600.c

3873

WREG32(CP_INT_CNTL, cp_int_cntl);