sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

185

cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

188

cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

191

cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

194

cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

53

static struct mpll_cfg dcn21_mpll_cfg_ref[] = {

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

225

cfg->mpll_cfg = dcn2_mpll_cfg[0];

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

228

cfg->mpll_cfg = dcn2_mpll_cfg[1];

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

231

cfg->mpll_cfg = dcn2_mpll_cfg[2];

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

234

cfg->mpll_cfg = dcn2_mpll_cfg[3];

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

58

static struct mpll_cfg dcn2_mpll_cfg[] = {

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

292

struct mpll_cfg mpll_cfg;