sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9131

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9137

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9259

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9305

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6392

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6394

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6400

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6402

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6525

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6571

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6712

tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6722

tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4768

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4770

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4776

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4778

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4901

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4947

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6503

WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5987

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5993

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6048

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6084

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3103

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3109

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3166

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3206

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

sys/dev/pci/drm/radeon/cik.c

6868

WREG32(CP_ME1_PIPE0_INT_CNTL, 0);

sys/dev/pci/drm/radeon/cik.c

7051

cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

sys/dev/pci/drm/radeon/cik.c

7222

WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);