Symbol: mpcc
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
62
static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
64
mpcc->mpcc_id = mpcc_inst;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
65
mpcc->dpp_id = 0xf;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
66
mpcc->mpcc_bot = NULL;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
67
mpcc->blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
68
mpcc->blnd_cfg.global_alpha = 0xff;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
69
mpcc->blnd_cfg.global_gain = 0xff;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
70
mpcc->blnd_cfg.background_color_bpc = 4;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
71
mpcc->blnd_cfg.bottom_gain_mode = 0;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
72
mpcc->blnd_cfg.top_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
73
mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
74
mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
75
mpcc->sm_cfg.enable = false;
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
76
mpcc->shared_bottom = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1449
struct mpcc *mpcc_to_remove = NULL;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2893
struct mpcc *new_mpcc;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1525
new_pipe->update_flags.bits.mpcc = 1;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1602
new_pipe->update_flags.bits.mpcc = 1;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1765
if (pipe_ctx->update_flags.bits.mpcc
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2939
struct mpcc *new_mpcc;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2986
!pipe_ctx->update_flags.bits.mpcc) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
384
struct mpcc *mpcc_to_remove = NULL;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
428
struct mpcc *new_mpcc;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
429
struct mpcc *remove_mpcc = NULL;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1466
phantom_pipe->update_flags.bits.mpcc = 1;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2495
new_pipe->update_flags.bits.mpcc = 1;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2571
new_pipe->update_flags.bits.mpcc = 1;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
409
uint32_t mpcc : 1;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
287
struct mpcc *mpcc_bot;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
321
struct mpcc *opp_list;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
328
struct mpcc mpcc_array[MAX_MPCC];
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
399
struct mpcc* (*insert_plane)(
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
404
struct mpcc *insert_above_mpcc,
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
426
struct mpcc *mpcc);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
520
struct mpcc* (*insert_plane_to_secondary)(
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
525
struct mpcc *insert_above_mpcc,
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
547
struct mpcc *mpcc);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
563
struct mpcc* (*get_mpcc_for_dpp_from_secondary)(
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
581
struct mpcc* (*get_mpcc_for_dpp)(
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
232
int mpcc[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
119
struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
127
struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
129
struct mpcc *tmp_mpcc = tree->opp_list;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
179
struct mpcc *mpc1_insert_plane(
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
184
struct mpcc *insert_above_mpcc,
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
189
struct mpcc *new_mpcc = NULL;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
197
struct mpcc *temp_mpcc = tree->opp_list;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
233
struct mpcc *temp_mpcc = tree->opp_list;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
274
struct mpcc *mpcc_to_remove)
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
294
struct mpcc *temp_mpcc = tree->opp_list;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
336
static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
338
mpcc->mpcc_id = mpcc_inst;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
339
mpcc->dpp_id = 0xf;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
340
mpcc->mpcc_bot = NULL;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
341
mpcc->blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
342
mpcc->blnd_cfg.global_alpha = 0xff;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
343
mpcc->blnd_cfg.global_gain = 0xff;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
344
mpcc->sm_cfg.enable = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
405
struct mpcc *mpcc;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
421
mpcc = mpc1_get_mpcc(mpc, mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
422
mpcc->dpp_id = top_sel;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
426
tree->opp_list = mpcc;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
432
struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
434
mpcc->mpcc_bot = mpcc_bottom;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
45
struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
82
struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
91
mpcc->blnd_cfg = *blnd_cfg;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
141
struct mpcc *mpc1_insert_plane(
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
146
struct mpcc *insert_above_mpcc,
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
153
struct mpcc *mpcc);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
184
struct mpcc *mpc1_get_mpcc(
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
188
struct mpcc *mpc1_get_mpcc_for_dpp(
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
509
static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
511
mpcc->mpcc_id = mpcc_inst;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
512
mpcc->dpp_id = 0xf;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
513
mpcc->mpcc_bot = NULL;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
514
mpcc->blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
515
mpcc->blnd_cfg.global_alpha = 0xff;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
516
mpcc->blnd_cfg.global_gain = 0xff;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
517
mpcc->blnd_cfg.background_color_bpc = 4;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
518
mpcc->blnd_cfg.bottom_gain_mode = 0;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
519
mpcc->blnd_cfg.top_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
520
mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
521
mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
522
mpcc->sm_cfg.enable = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
525
static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
527
struct mpcc *tmp_mpcc = tree->opp_list;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
55
struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
70
mpcc->blnd_cfg = *blnd_cfg;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1049
void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1051
mpcc->mpcc_id = mpcc_inst;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1052
mpcc->dpp_id = 0xf;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1053
mpcc->mpcc_bot = NULL;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1054
mpcc->blnd_cfg.overlap_only = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1055
mpcc->blnd_cfg.global_alpha = 0xff;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1056
mpcc->blnd_cfg.global_gain = 0xff;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1057
mpcc->blnd_cfg.background_color_bpc = 4;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1058
mpcc->blnd_cfg.bottom_gain_mode = 0;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1059
mpcc->blnd_cfg.top_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1060
mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1061
mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1062
mpcc->sm_cfg.enable = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1063
mpcc->shared_bottom = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
1099
void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);