sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

823

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

521

if (adev->dm.dc->caps.color.mpc.ogam_ram)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1637

if (dm->dc->caps.color.mpc.gamut_remap)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1641

if (dpp_color_caps.hw_3d_lut || dm->dc->caps.color.mpc.preblend) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1072

struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1076

if (mpc->funcs->power_on_mpc_mem_pwr)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1077

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1082

struct mpc *mpc = params->set_output_csc_params.mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1087

if (mpc->funcs->set_output_csc != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1088

mpc->funcs->set_output_csc(mpc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1096

struct mpc *mpc = params->set_ocsc_default_params.mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1101

if (mpc->funcs->set_ocsc_default != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1102

mpc->funcs->set_ocsc_default(mpc,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1249

dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

855

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

862

block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

869

block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3701

if (pool->mpc->funcs->read_mpcc_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3704

pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3707

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3711

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3712

&pool->mpc->mpcc_array[s.bot_mpcc_id];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

884

unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

928

unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts;

sys/dev/pci/drm/amd/display/dc/dc.h

265

struct mpc_color_caps mpc;

sys/dev/pci/drm/amd/display/dc/dc.h

767

bool mpc: 1;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

398

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c

43

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c

49

struct dcn201_mpc *mpc201 = TO_DCN201_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h

71

struct mpc base;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1447

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1453

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1459

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1635

dc->res_pool->mpc->funcs->mpc_init_single_inst(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1636

dc->res_pool->mpc, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2260

dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2880

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2882

if (mpc->funcs->set_bg_color) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2883

mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2894

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2935

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2941

new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2944

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2947

mpc->funcs->assert_mpcc_idle_before_connect(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2948

dc->res_pool->mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2951

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3576

res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

541

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

550

dc->caps.color.mpc.gamut_remap,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

551

dc->caps.color.mpc.num_3dluts,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

552

dc->caps.color.mpc.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

553

dc->caps.color.mpc.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

564

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

599

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1007

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1011

if (mpc->funcs->power_on_mpc_mem_pwr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1012

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1015

if (mpc->funcs->set_output_csc != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1016

mpc->funcs->set_output_csc(mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1021

if (mpc->funcs->set_ocsc_default != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1022

mpc->funcs->set_ocsc_default(mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1033

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1042

if (mpc->funcs->power_on_mpc_mem_pwr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1043

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1045

&& mpc->funcs->set_output_gamma) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1052

&mpc->blender_params, false))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1053

params = &mpc->blender_params;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1063

if (mpc->funcs->set_output_gamma)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1064

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

171

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

183

dc->caps.color.mpc.gamut_remap,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

184

dc->caps.color.mpc.num_3dluts,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

185

dc->caps.color.mpc.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

186

dc->caps.color.mpc.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2940

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2987

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2993

new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2996

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2999

mpc->funcs->assert_mpcc_idle_before_connect(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3000

dc->res_pool->mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3003

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3184

res_pool->mpc->funcs->mpc_init(res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

845

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

938

if (mpc->funcs->set_out_rate_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

940

mpc->funcs->set_out_rate_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

941

mpc, opp_inst[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

294

res_pool->mpc->funcs->mpc_init(res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

382

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

391

if (mpc->funcs->get_mpcc_for_dpp_from_secondary)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

392

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp_from_secondary(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

395

if (mpcc_to_remove != NULL && mpc->funcs->remove_mpcc_from_secondary) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

396

mpc->funcs->remove_mpcc_from_secondary(mpc, mpc_tree_params, mpcc_to_remove);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

401

mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

403

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

430

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

487

mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

492

if (mpc->funcs->get_mpcc_for_dpp_from_secondary)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

493

remove_mpcc = mpc->funcs->get_mpcc_for_dpp_from_secondary(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

496

if (remove_mpcc != NULL && mpc->funcs->remove_mpcc_from_secondary)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

497

mpc->funcs->remove_mpcc_from_secondary(mpc, mpc_tree_params, remove_mpcc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

500

remove_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

504

mpc->funcs->remove_mpcc(mpc, mpc_tree_params, remove_mpcc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

507

mpc->funcs->assert_mpcc_idle_before_connect(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

508

dc->res_pool->mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

512

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

182

pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

183

mpc3_get_gamut_remap(pool->mpc, i, &s.gamut_remap);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

225

dc->caps.color.mpc.gamut_remap,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

226

dc->caps.color.mpc.num_3dluts,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

227

dc->caps.color.mpc.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

228

dc->caps.color.mpc.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

259

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

290

acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

295

result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

300

result = mpc->funcs->program_shaper(mpc, shaper_lut,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

307

mpc->funcs->release_rmu(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

360

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

388

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

396

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

404

if (ret == false && mpc->funcs->set_output_gamma) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

411

&mpc->blender_params, false))

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

412

params = &mpc->blender_params;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

419

if (mpc->funcs->set_output_gamma)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

420

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

443

dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

569

dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

93

if (dc->debug.enable_mem_low_power.bits.mpc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

94

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

95

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

179

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

193

if (mpc->funcs->set_out_rate_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

195

mpc->funcs->set_out_rate_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

196

mpc, opp_inst[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

445

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

464

result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

468

result = mpc->funcs->program_shaper(mpc, shaper_lut, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

481

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

497

mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

511

mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

515

result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

517

result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

527

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

534

if (mpc == NULL || plane_state == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

567

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

575

if (ret == false && mpc->funcs->set_output_gamma) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

582

&mpc->blender_params, false))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

583

params = &mpc->blender_params;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

590

if (mpc->funcs->set_output_gamma)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

591

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

100

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

101

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

435

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

449

if (mpc->funcs->set_out_rate_control) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

451

mpc->funcs->set_out_rate_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

452

mpc, opp_inst[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

687

dc->res_pool->mpc->funcs->mpc_init_single_inst(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

688

dc->res_pool->mpc, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

99

if (dc->debug.enable_mem_low_power.bits.mpc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

111

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

117

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

133

mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

379

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

386

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

413

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

436

rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

442

if (mpc->funcs->populate_lut)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

443

mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

445

if (mpc->funcs->program_lut_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

446

mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

456

rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

462

if (mpc->funcs->mcm.populate_lut)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

463

mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

464

if (mpc->funcs->program_lut_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

465

mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

478

if (mpc->funcs->populate_lut)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

479

mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

480

if (mpc->funcs->program_lut_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

481

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

499

if (mpc->funcs->mcm.is_config_supported &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

500

!mpc->funcs->mcm.is_config_supported(width))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

503

if (mpc->funcs->program_lut_read_write_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

504

mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

505

if (mpc->funcs->program_lut_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

506

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

511

if (mpc->funcs->mcm.program_bit_depth)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

512

mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

552

mpc->funcs->mcm.program_bias_scale) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

553

mpc->funcs->mcm.program_bias_scale(mpc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

579

if (mpc->funcs->mcm.program_lut_read_write_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

580

mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

582

if (mpc->funcs->mcm.program_3dlut_size)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

583

mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

585

if (mpc->funcs->update_3dlut_fast_load_select)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

586

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

591

if (mpc->funcs->program_lut_mode) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

592

mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

593

mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

594

mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

617

struct mpc *mpc = dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

627

mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

638

result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

651

result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

654

if (mpc->funcs->program_3dlut) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

656

result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

658

result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

669

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

677

if (ret == false && mpc->funcs->set_output_gamma) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

684

&mpc->blender_params, false))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

685

params = &mpc->blender_params;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

692

if (mpc->funcs->set_output_gamma)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

693

mpc->funcs->set_output_gamma(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

92

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

121

struct mpc *mpc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

127

struct mpc *mpc;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

134

struct mpc *mpc;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

253

struct mpc *mpc;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1000

void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1016

void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1034

void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1052

void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1070

void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1079

void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1080

void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1081

void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1083

void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1086

void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1096

void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1097

void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1098

void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1099

void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1101

void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_XABLE xable,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1103

void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1104

void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1105

void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1108

void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1109

void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

373

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

400

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

424

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

441

void (*mpc_init)(struct mpc *mpc);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

453

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

472

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

493

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

521

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

545

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

598

void (*wait_for_idle)(struct mpc *mpc, int id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

613

void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

630

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

648

void (*set_denorm)(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

667

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

687

void (*set_output_csc)(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

709

void (*set_ocsc_default)(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

730

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

750

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

769

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

788

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

806

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

826

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

847

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

864

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

883

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

901

uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

916

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

933

int (*release_rmu)(struct mpc *mpc, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

949

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

967

void (*set_bg_color)(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

984

void (*set_mpc_mem_lp_mode)(struct mpc *mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

109

void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

111

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

119

struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

121

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

124

return &(mpc->mpcc_array[mpcc_id]);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

145

void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

147

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

180

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

188

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

207

new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

247

mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

252

mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

272

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

276

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

355

void mpc1_mpc_init(struct mpc *mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

357

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

368

mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

377

void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

379

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

389

mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

397

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

40

void mpc1_set_bg_color(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

400

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

421

mpcc = mpc1_get_mpcc(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

432

struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

44

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

443

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

447

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

45

struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

460

void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

462

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

467

unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

469

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

77

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

81

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

82

struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

95

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

99

struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

125

struct mpc base;

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

142

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

151

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

156

struct mpc *mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

159

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

163

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

167

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

172

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

177

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

181

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

185

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

193

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

197

void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

199

unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

112

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

116

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

132

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

138

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

186

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

192

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

245

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

248

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

273

struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

276

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

284

struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

287

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

296

static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

300

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

322

static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

325

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

328

mpc2_ogam_get_reg_field(mpc, &gam_regs);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

349

static void mpc2_program_luta(struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

352

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

355

mpc2_ogam_get_reg_field(mpc, &gam_regs);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

377

struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

382

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

406

static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

410

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

412

if (mpc->ctx->dc->debug.cm_in_bypass) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

417

if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

431

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

437

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

439

if (mpc->ctx->dc->debug.cm_in_bypass) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

449

current_mode = mpc20_get_ogam_current(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

455

mpc20_power_on_ogam_lut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

456

mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

459

mpc2_program_luta(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

461

mpc2_program_lutb(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

463

apply_DEDCN20_305_wa(mpc, mpcc_id, current_mode, next_mode);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

466

mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

471

void mpc2_assert_idle_mpcc(struct mpc *mpc, int id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

473

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

486

void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

488

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

49

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

53

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

544

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

548

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

55

struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

74

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

78

struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

261

struct mpc base;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

278

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

283

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

288

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

293

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

299

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

305

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

309

void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

310

void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

311

void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1003

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1028

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1034

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

104

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

107

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1126

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1130

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

114

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1198

void mpc3_get_gamut_remap(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

120

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1202

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1219

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1234

mpc3_set_3dlut_mode(mpc, LUT_BYPASS, false, false, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1237

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1239

mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1268

mpc3_select_3dlut_ram(mpc, mode,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1270

mpc3_select_3dlut_ram_mask(mpc, 0x1, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1272

mpc3_set3dlut_ram12(mpc, lut0, lut_size0, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1274

mpc3_set3dlut_ram10(mpc, lut0, lut_size0, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1276

mpc3_select_3dlut_ram_mask(mpc, 0x2, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1278

mpc3_set3dlut_ram12(mpc, lut1, lut_size, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1280

mpc3_set3dlut_ram10(mpc, lut1, lut_size, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1282

mpc3_select_3dlut_ram_mask(mpc, 0x4, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1284

mpc3_set3dlut_ram12(mpc, lut2, lut_size, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1286

mpc3_set3dlut_ram10(mpc, lut2, lut_size, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1288

mpc3_select_3dlut_ram_mask(mpc, 0x8, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1290

mpc3_set3dlut_ram12(mpc, lut3, lut_size, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1292

mpc3_set3dlut_ram10(mpc, lut3, lut_size, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1294

mpc3_set_3dlut_mode(mpc, mode, is_12bits_color_channel,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1297

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1298

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

130

enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1304

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1309

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1343

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1348

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

138

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1387

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1391

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1401

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1405

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1415

uint32_t mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1420

rmu_status = mpc3_get_rmu_mux_status(mpc, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1426

mpc3_set_rmu_mux(mpc, rmu_idx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1434

static int mpcc3_release_rmu(struct mpc *mpc, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1436

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1442

rmu_status = mpc3_get_rmu_mux_status(mpc, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1444

mpc3_set_rmu_mux(mpc, rmu_idx, 0xf);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1453

static void mpc3_set_mpc_mem_lp_mode(struct mpc *mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1455

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1458

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1472

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1476

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

169

struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

172

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

189

struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

192

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

202

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

205

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

235

static void mpc3_program_luta(struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

238

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

241

mpc3_ogam_get_reg_field(mpc, &gam_regs);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

268

static void mpc3_program_lutb(struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

271

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

274

mpc3_ogam_get_reg_field(mpc, &gam_regs);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

303

struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

308

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

342

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

348

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

350

if (mpc->ctx->dc->debug.cm_in_bypass) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

362

current_mode = mpc3_get_ogam_current(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

370

mpc3_power_on_ogam_lut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

371

mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

374

mpc3_program_luta(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

376

mpc3_program_lutb(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

379

mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

385

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

386

mpc3_power_on_ogam_lut(mpc, mpcc_id, false);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

390

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

394

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

429

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

433

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

447

static enum dc_lut_mode mpc3_get_shaper_current(struct mpc *mpc, uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

451

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

47

void mpc3_mpc_init(struct mpc *mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

474

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

478

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

488

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

49

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

493

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

52

mpc1_mpc_init(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

62

void mpc3_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

637

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

64

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

642

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

66

mpc1_mpc_init_single_inst(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

78

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

788

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

797

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

81

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

821

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

827

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

834

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

845

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

864

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

871

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

878

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

879

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

881

current_mode = mpc3_get_shaper_current(mpc, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

888

mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

891

mpc3_program_shaper_luta_settings(mpc, params, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

893

mpc3_program_shaper_lutb_settings(mpc, params, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

896

mpc, params->rgb_resulted, params->hw_points_num, rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

899

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

905

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

912

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

927

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

93

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

934

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

97

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

972

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

977

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

985

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

989

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

997

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1011

struct mpc *mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1014

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1018

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1023

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1027

uint32_t mpcc3_acquire_rmu(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1031

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1036

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1041

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1047

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1053

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1058

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1062

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1066

void mpc3_get_gamut_remap(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1071

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1076

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1081

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1085

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1089

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1096

struct mpc *mpc, int mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1102

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

992

struct mpc base;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

125

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

129

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

140

struct dcn30_mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

143

reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

144

reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

145

reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

146

reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

147

reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

148

reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

149

reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

150

reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

152

reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

153

reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

154

reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

155

reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

156

reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

157

reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

158

reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

159

reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

160

reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

161

reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

162

reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

163

reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

168

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

172

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

192

cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

197

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

201

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

221

cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

225

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

231

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

262

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

268

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

272

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

273

mpc32_power_on_blnd_lut(mpc, mpcc_id, false);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

277

current_mode = mpc32_get_post1dlut_current(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

283

mpc32_power_on_blnd_lut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

284

mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

287

mpc32_program_post1dluta_settings(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

289

mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

292

mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

301

static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

305

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

329

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

333

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

344

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

349

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

45

void mpc32_mpc_init(struct mpc *mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

47

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

496

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

50

mpc3_mpc_init(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

501

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

52

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

649

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

658

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

68

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

683

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

689

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

695

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

713

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

72

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

720

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

727

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

729

current_mode = mpc32_get_shaper_current(mpc, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

736

mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

739

mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

741

mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

744

mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

747

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

754

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

76

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

761

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

80

} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

800

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

805

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

814

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

818

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

827

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

833

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

859

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

865

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

881

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

888

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

908

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

92

static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

923

mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

926

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

928

mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

957

mpc32_select_3dlut_ram(mpc, mode,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

959

mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

961

mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

963

mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

965

mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

967

mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

969

mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

971

mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

973

mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

975

mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

977

mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

979

mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

98

struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

981

mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

983

mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

986

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

987

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

311

void mpc32_mpc_init(struct mpc *mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

313

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

317

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

321

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

334

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

338

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

343

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

347

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

351

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

355

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

360

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

364

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

368

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

372

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

376

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

381

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

386

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

390

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

396

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

111

void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

131

mpc32_power_on_blnd_lut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

132

mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

135

mpc32_program_post1dluta_settings(mpc, mpcc_id, lut1d);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

137

mpc32_program_post1dlutb_settings(mpc, mpcc_id, lut1d);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

140

mpc, mpcc_id, lut1d->rgb_resulted, lut1d->hw_points_num);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

146

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

147

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

149

mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

152

mpc32_program_shaper_luta_settings(mpc, lut_shaper, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

154

mpc32_program_shaper_lutb_settings(mpc, lut_shaper, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

157

mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

159

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

165

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

167

get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

191

mpc32_select_3dlut_ram(mpc, next_mode,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

193

mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

195

mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

197

mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

199

mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

201

mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

203

mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

205

mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

207

mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

209

mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

211

mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

213

mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

215

mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

217

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

218

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

226

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

232

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

272

void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

274

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

278

mpc32_select_3dlut_ram_mask(mpc, 0xf, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

282

mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

285

mpc32_configure_post1dlut(mpc, lut_bank_a, mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

291

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

298

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

328

mpc->ctx,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

362

mpc->ctx,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

397

mpc->ctx,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

412

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

416

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

422

mpc_program_gamut_remap(mpc, mpcc_id, NULL,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

43

void mpc401_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

45

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

456

mpc_program_gamut_remap(mpc, mpcc_id, arr_reg_val,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

461

void mpc_read_gamut_remap(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

468

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

50

void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

52

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

552

void mpc401_get_gamut_remap(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

559

mpc_read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

67

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

74

struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

190

struct mpc base;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

207

void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

208

void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

212

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

219

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

225

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

230

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

235

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

240

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

246

void mpc_read_gamut_remap(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

253

struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1388

dc->caps.color.mpc.gamut_remap = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1389

dc->caps.color.mpc.num_3dluts = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1390

dc->caps.color.mpc.shared_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1391

dc->caps.color.mpc.ogam_ram = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1392

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1393

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1394

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1395

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1396

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1397

dc->caps.color.mpc.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1639

pool->base.mpc = dcn10_mpc_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1640

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

668

static struct mpc *dcn10_mpc_create(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

911

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

912

kfree(TO_DCN10_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

913

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1098

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1099

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1100

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2463

dc->caps.color.mpc.gamut_remap = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2464

dc->caps.color.mpc.num_3dluts = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2465

dc->caps.color.mpc.shared_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2466

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2467

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2468

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2469

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2470

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2471

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2472

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2681

pool->base.mpc = dcn20_mpc_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2682

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

836

struct mpc *dcn20_mpc_create(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

111

struct mpc *dcn20_mpc_create(struct dc_context *ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1144

dc->caps.color.mpc.gamut_remap = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1145

dc->caps.color.mpc.num_3dluts = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1146

dc->caps.color.mpc.shared_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1147

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1148

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1149

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1150

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1151

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1152

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1153

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1265

pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1266

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

724

static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

922

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

923

kfree(TO_DCN201_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

924

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1062

static struct mpc *dcn21_mpc_create(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1449

dc->caps.color.mpc.gamut_remap = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1450

dc->caps.color.mpc.num_3dluts = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1451

dc->caps.color.mpc.shared_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1452

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1453

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1454

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1455

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1456

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1457

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1458

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1642

pool->base.mpc = dcn21_mpc_create(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1643

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

669

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

670

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

671

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1089

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1090

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1091

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2344

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2345

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2346

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2347

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2348

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2349

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2350

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2351

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2352

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2528

pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2529

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

838

static struct mpc *dcn30_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1060

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1061

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1062

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1473

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1474

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1475

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1476

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1477

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1478

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1479

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1480

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1481

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1648

pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1649

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

793

static struct mpc *dcn301_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1012

if (pool->mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1013

kfree(TO_DCN20_MPC(pool->mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1014

pool->mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1264

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1265

dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1266

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1267

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1268

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1269

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1270

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1271

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1272

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1426

pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1427

if (pool->mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

649

static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1208

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1209

dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1210

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1211

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1212

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1213

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1214

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1215

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1216

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1358

pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1359

if (pool->mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

613

static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

956

if (pool->mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

957

kfree(TO_DCN20_MPC(pool->mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

958

pool->mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1001

static struct mpc *dcn31_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1390

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1391

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1392

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1949

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1950

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1951

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1952

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1953

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1954

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1955

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1956

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1957

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2136

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2137

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

884

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1059

static struct mpc *dcn31_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1449

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1450

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1451

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1880

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1881

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1882

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1883

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1884

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1885

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1886

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1887

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1888

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2060

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2061

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

904

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1390

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1391

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1392

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1917

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1918

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1919

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1920

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1921

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1922

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1923

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1924

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1925

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2084

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2085

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

884

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

999

static struct mpc *dcn31_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1386

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1387

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1388

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1793

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1794

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1795

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1796

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1797

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1798

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1799

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1800

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1801

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1952

pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1953

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

879

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

993

static struct mpc *dcn31_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1396

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1397

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1398

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2268

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2269

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2270

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2271

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2272

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2273

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2274

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2275

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2276

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2277

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2444

pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2445

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

714

.mpc = false,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

946

static struct mpc *dcn32_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1377

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1378

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1379

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1768

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1769

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1770

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1771

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1772

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1773

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1774

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1775

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1776

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1777

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1939

pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1940

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

710

.mpc = false,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

940

static struct mpc *dcn321_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1459

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1460

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1461

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1903

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1904

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1905

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1906

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1907

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1908

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1909

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1910

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1911

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1912

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2105

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2106

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

744

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

949

static struct mpc *dcn35_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1439

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1440

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1441

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1876

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1877

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1878

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1879

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1880

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1881

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1882

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1883

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1884

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1885

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2077

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2078

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

724

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

929

static struct mpc *dcn35_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1440

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1441

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1442

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1876

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1877

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1878

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1879

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1880

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1881

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1882

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1883

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1884

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1885

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2078

pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2079

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

725

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

930

static struct mpc *dcn35_mpc_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1399

if (pool->base.mpc != NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1400

kfree(TO_DCN20_MPC(pool->base.mpc));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1401

pool->base.mpc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1946

dc->caps.color.mpc.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1947

dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1948

dc->caps.color.mpc.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1949

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1950

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1951

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1952

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1953

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1954

dc->caps.color.mpc.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1955

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2134

pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2135

if (pool->base.mpc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

705

.mpc = false,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

939

static struct mpc *dcn401_mpc_create(

sys/dev/pci/if_em_hw.h

1326

uint64_t mpc;

sys/dev/pci/if_ixgb.c

1941

sc->stats.mpc += IXGB_READ_REG(&sc->hw, MPC);

sys/dev/pci/if_ixgb.c

2002

sc->stats.mpc +

sys/dev/pci/if_ixgb.c

2056

(long long)sc->stats.mpc);

sys/dev/pci/ixgb_hw.h

778

uint64_t mpc;

sys/dev/pci/ixgbe_type.h

3815

uint64_t mpc[8];

sys/dev/sbus/qereg.h

210

u_int8_t mpc; [24] /* missed packet count */