sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

330

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

255

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

241

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

226

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

269

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6973

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6975

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6978

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6980

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6981

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6983

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6984

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4295

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4297

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4299

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4300

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4303

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4304

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4307

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3173

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3175

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3177

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3178

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3180

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3181

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3184

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4452

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4454

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4457

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4459

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4460

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4461

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4462

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3624

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3626

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3629

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3631

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3632

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3633

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3634

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1903

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1905

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1908

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1910

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1911

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1912

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1913

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1164

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1166

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1168

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1169

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1170

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1171

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1172

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1324

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1326

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1328

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1329

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1330

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1331

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1332

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

sys/dev/pci/drm/radeon/cik.c

4658

mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);

sys/dev/pci/drm/radeon/cik.c

4673

WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);