sys/dev/pci/drm/amd/amdgpu/cik.c

1006

WREG32(mmVGA_RENDER_CONTROL, vga_render_control);

sys/dev/pci/drm/amd/amdgpu/cik.c

980

vga_render_control = RREG32(mmVGA_RENDER_CONTROL);

sys/dev/pci/drm/amd/amdgpu/cik.c

994

WREG32(mmVGA_RENDER_CONTROL,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

457

tmp = RREG32(mmVGA_RENDER_CONTROL);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

462

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

414

WREG32(mmVGA_RENDER_CONTROL,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

415

RREG32(mmVGA_RENDER_CONTROL) & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

408

tmp = RREG32(mmVGA_RENDER_CONTROL);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

413

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

251

tmp = RREG32(mmVGA_RENDER_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

253

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

288

tmp = RREG32(mmVGA_RENDER_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

290

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

463

tmp = RREG32(mmVGA_RENDER_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

465

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/pci/drm/amd/amdgpu/si.c

1285

vga_render_control = RREG32(mmVGA_RENDER_CONTROL);

sys/dev/pci/drm/amd/amdgpu/si.c

1299

WREG32(mmVGA_RENDER_CONTROL,

sys/dev/pci/drm/amd/amdgpu/si.c

1311

WREG32(mmVGA_RENDER_CONTROL, vga_render_control);

sys/dev/pci/drm/amd/amdgpu/vi.c

602

vga_render_control = RREG32(mmVGA_RENDER_CONTROL);

sys/dev/pci/drm/amd/amdgpu/vi.c

616

WREG32(mmVGA_RENDER_CONTROL,

sys/dev/pci/drm/amd/amdgpu/vi.c

628

WREG32(mmVGA_RENDER_CONTROL, vga_render_control);