Symbol: mmVCE_VCPU_CACHE_OFFSET1
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
192
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
579
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
588
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
289
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
671
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24));