sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

174

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

329

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

331

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

345

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

347

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

377

orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

380

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

383

WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

197

data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

199

WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

221

data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

223

WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

555

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

637

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);