sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

122

uint32_t status = RREG32(mmVCE_STATUS);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

236

WREG32_P(mmVCE_STATUS, 1, ~1);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

265

WREG32_P(mmVCE_STATUS, 0, ~1);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

311

WREG32(mmVCE_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

241

uint32_t status = RREG32(mmVCE_STATUS);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

351

WREG32(mmVCE_STATUS, 0);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

649

if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

654

if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

132

RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

305

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

312

MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

317

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

366

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

378

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

400

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0);