sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

245

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

77

return RREG32(mmVCE_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

94

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

122

v = RREG32(mmVCE_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

153

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

282

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

115

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

344

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

89

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));